2011-01-18 23:30:06 +01:00
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---------- Begin Simulation Statistics ----------
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2011-02-23 22:10:50 +01:00
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host_inst_rate 52926 # Simulator instruction rate (inst/s)
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host_mem_usage 260544 # Number of bytes of host memory used
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host_seconds 3491.51 # Real time elapsed on the host
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host_tick_rate 42909528 # Simulator tick rate (ticks/s)
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2011-01-18 23:30:06 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-02-23 22:10:50 +01:00
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sim_insts 184792363 # Number of instructions simulated
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2011-01-18 23:30:06 +01:00
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sim_seconds 0.149819 # Number of seconds simulated
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2011-02-23 22:10:50 +01:00
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sim_ticks 149819214000 # Number of ticks simulated
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2011-01-18 23:30:06 +01:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.BTBHits 51777441 # Number of BTB hits
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2011-02-23 22:10:50 +01:00
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system.cpu.BPredUnit.BTBLookups 55728820 # Number of BTB lookups
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2011-01-18 23:30:06 +01:00
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system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
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system.cpu.BPredUnit.condIncorrect 12604932 # Number of conditional branches incorrect
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2011-02-23 22:10:50 +01:00
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system.cpu.BPredUnit.condPredicted 57019635 # Number of conditional branches predicted
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system.cpu.BPredUnit.lookups 57019635 # Number of BP lookups
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2011-01-18 23:30:06 +01:00
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system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
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system.cpu.commit.COM:branches 39499925 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 586569 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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2011-02-23 22:10:50 +01:00
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system.cpu.commit.COM:committed_per_cycle::samples 285162046 # Number of insts commited each cycle
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2011-01-18 23:30:06 +01:00
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system.cpu.commit.COM:committed_per_cycle::mean 0.648076 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::stdev 0.934649 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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2011-02-23 22:10:50 +01:00
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system.cpu.commit.COM:committed_per_cycle::0 151201890 53.02% 53.02% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::1 102481075 35.94% 88.96% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::2 22788718 7.99% 96.95% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::3 3864443 1.36% 98.31% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::4 2118451 0.74% 99.05% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::5 1126210 0.39% 99.45% # Number of insts commited each cycle
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2011-01-18 23:30:06 +01:00
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system.cpu.commit.COM:committed_per_cycle::6 605325 0.21% 99.66% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::7 389365 0.14% 99.79% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::8 586569 0.21% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
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2011-02-23 22:10:50 +01:00
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system.cpu.commit.COM:committed_per_cycle::total 285162046 # Number of insts commited each cycle
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2011-01-18 23:30:06 +01:00
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system.cpu.commit.COM:count 184806751 # Number of instructions committed
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2011-02-08 04:23:13 +01:00
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system.cpu.commit.COM:fp_insts 1730659 # Number of committed floating point instructions.
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system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
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system.cpu.commit.COM:int_insts 146860811 # Number of committed integer instructions.
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2011-01-18 23:30:06 +01:00
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system.cpu.commit.COM:loads 29554611 # Number of loads committed
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system.cpu.commit.COM:membars 0 # Number of memory barriers committed
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system.cpu.commit.COM:refs 42081439 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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2011-02-23 22:10:50 +01:00
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system.cpu.commit.branchMispredicts 12955566 # The number of times a branch was mispredicted
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2011-01-18 23:30:06 +01:00
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system.cpu.commit.commitCommittedInsts 184806751 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 1569953 # The number of times commit has been forced to stall to communicate backwards
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2011-02-23 22:10:50 +01:00
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system.cpu.commit.commitSquashedInsts 36913868 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 184792363 # Number of Instructions Simulated
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system.cpu.committedInsts_total 184792363 # Number of Instructions Simulated
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system.cpu.cpi 1.621487 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 1.621487 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_accesses 32436973 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 31572.057898 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32361.072902 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 32435384 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 50168000 # number of ReadReq miss cycles
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.ReadReq_miss_rate 0.000049 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 1589 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 862 # number of ReadReq MSHR hits
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2011-02-23 22:10:50 +01:00
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system.cpu.dcache.ReadReq_mshr_miss_latency 23526500 # number of ReadReq MSHR miss cycles
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 727 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 12273971 # number of WriteReq accesses(hits+misses)
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2011-02-23 22:10:50 +01:00
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system.cpu.dcache.WriteReq_avg_miss_latency 25388.039035 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35046.660567 # average WriteReq mshr miss latency
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.WriteReq_hits 12266388 # number of WriteReq hits
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2011-02-23 22:10:50 +01:00
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system.cpu.dcache.WriteReq_miss_latency 192517500 # number of WriteReq miss cycles
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.WriteReq_miss_rate 0.000618 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 7583 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 6490 # number of WriteReq MSHR hits
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2011-02-23 22:10:50 +01:00
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system.cpu.dcache.WriteReq_mshr_miss_latency 38306000 # number of WriteReq MSHR miss cycles
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.000089 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 1093 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets 9000 # average number of cycles each access was blocked
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2011-02-23 22:10:50 +01:00
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system.cpu.dcache.avg_refs 24561.413187 # Average number of references to valid blocks.
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 9000 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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2011-02-23 22:10:50 +01:00
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system.cpu.dcache.demand_accesses 44710944 # number of demand (read+write) accesses
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.demand_avg_miss_latency 26459.387266 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 33973.901099 # average overall mshr miss latency
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2011-02-23 22:10:50 +01:00
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system.cpu.dcache.demand_hits 44701772 # number of demand (read+write) hits
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.demand_miss_latency 242685500 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.000205 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 9172 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 7352 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 61832500 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.000041 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 1820 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.occ_%::0 0.337576 # Average percentage of cache occupancy
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2011-02-23 22:10:50 +01:00
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system.cpu.dcache.occ_blocks::0 1382.712770 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses 44710944 # number of overall (read+write) accesses
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.overall_avg_miss_latency 26459.387266 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 33973.901099 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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2011-02-23 22:10:50 +01:00
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system.cpu.dcache.overall_hits 44701772 # number of overall hits
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.overall_miss_latency 242685500 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.000205 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 9172 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 7352 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 61832500 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.000041 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 1820 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 46 # number of replacements
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system.cpu.dcache.sampled_refs 1820 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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2011-02-23 22:10:50 +01:00
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system.cpu.dcache.tagsinuse 1382.712770 # Cycle average of tags in use
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system.cpu.dcache.total_refs 44701772 # Total number of references to valid blocks.
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 17 # number of writebacks
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2011-02-23 22:10:50 +01:00
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system.cpu.decode.DECODE:BlockedCycles 21645694 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:DecodedInsts 264148336 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 61114397 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 200863123 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 14403927 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:UnblockCycles 1538831 # Number of cycles decode is unblocking
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2011-01-18 23:30:06 +01:00
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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2011-02-23 22:10:50 +01:00
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system.cpu.fetch.Branches 57019635 # Number of branches that fetch encountered
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.CacheLines 24416320 # Number of cache lines fetched
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system.cpu.fetch.Cycles 213842486 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 1112165 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 254182972 # Number of instructions fetch has processed
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2011-02-23 22:10:50 +01:00
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system.cpu.fetch.MiscStallCycles 47096 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.SquashCycles 13195878 # Number of cycles fetch has spent squashing
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.branchRate 0.190295 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 24416320 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 51777441 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 0.848299 # Number of inst fetches per cycle
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2011-02-23 22:10:50 +01:00
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system.cpu.fetch.rateDist::samples 299565972 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 0.927730 # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::stdev 1.045167 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2011-02-23 22:10:50 +01:00
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system.cpu.fetch.rateDist::0 86216390 28.78% 28.78% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 186583671 62.28% 91.07% # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::2 11093729 3.70% 94.77% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 7887786 2.63% 97.40% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 1768857 0.59% 97.99% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 2263080 0.76% 98.75% # Number of instructions fetched each cycle (Total)
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2011-02-23 22:10:50 +01:00
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system.cpu.fetch.rateDist::6 1007503 0.34% 99.08% # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::7 913678 0.31% 99.39% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 1831278 0.61% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2011-02-23 22:10:50 +01:00
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system.cpu.fetch.rateDist::total 299565972 # Number of instructions fetched each cycle (Total)
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2011-02-08 04:23:13 +01:00
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system.cpu.fp_regfile_reads 2799107 # number of floating regfile reads
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system.cpu.fp_regfile_writes 2446180 # number of floating regfile writes
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2011-01-18 23:30:06 +01:00
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system.cpu.icache.ReadReq_accesses 24416320 # number of ReadReq accesses(hits+misses)
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2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 25130.564219 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 21980.432060 # average ReadReq mshr miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.ReadReq_hits 24412793 # number of ReadReq hits
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.icache.ReadReq_miss_latency 88635500 # number of ReadReq miss cycles
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000144 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_misses 3527 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits 333 # number of ReadReq MSHR hits
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 70205500 # number of ReadReq MSHR miss cycles
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000131 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 3194 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_refs 7643.329054 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.icache.demand_accesses 24416320 # number of demand (read+write) accesses
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.icache.demand_avg_miss_latency 25130.564219 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 21980.432060 # average overall mshr miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.demand_hits 24412793 # number of demand (read+write) hits
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.icache.demand_miss_latency 88635500 # number of demand (read+write) miss cycles
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.demand_miss_rate 0.000144 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_misses 3527 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 333 # number of demand (read+write) MSHR hits
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.icache.demand_mshr_miss_latency 70205500 # number of demand (read+write) MSHR miss cycles
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000131 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 3194 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.icache.occ_%::0 0.617996 # Average percentage of cache occupancy
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.icache.occ_blocks::0 1265.656561 # Average occupied blocks per context
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.overall_accesses 24416320 # number of overall (read+write) accesses
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.icache.overall_avg_miss_latency 25130.564219 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 21980.432060 # average overall mshr miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.overall_hits 24412793 # number of overall hits
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.icache.overall_miss_latency 88635500 # number of overall miss cycles
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.overall_miss_rate 0.000144 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_misses 3527 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 333 # number of overall MSHR hits
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.icache.overall_mshr_miss_latency 70205500 # number of overall MSHR miss cycles
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000131 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 3194 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.icache.replacements 1539 # number of replacements
|
|
|
|
|
system.cpu.icache.sampled_refs 3194 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.icache.tagsinuse 1265.656561 # Cycle average of tags in use
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.total_refs 24412793 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.idleCycles 72457 # Total number of cycles that the CPU has spent unscheduled due to idling
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iew.EXEC:branches 40333139 # Number of branches executed
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.iew.EXEC:nop 106308 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.EXEC:rate 0.675299 # Inst execution rate
|
|
|
|
|
system.cpu.iew.EXEC:refs 46706723 # number of memory reference insts executed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iew.EXEC:stores 12922741 # Number of stores executed
|
|
|
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.iew.WB:consumers 166977314 # num instructions consuming a value
|
|
|
|
|
system.cpu.iew.WB:count 199432136 # cumulative count of insts written-back
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iew.WB:fanout 0.694920 # average fanout of values written-back
|
|
|
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.iew.WB:producers 116035928 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.WB:rate 0.665576 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.WB:sent 200401741 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.branchMispredicts 13076652 # Number of branch mispredicts detected at execute
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iew.iewBlockCycles 1256 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 37075609 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 1668755 # Number of dispatched non-speculative instructions
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.iew.iewDispSquashedInsts 11833619 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 14988549 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 221729626 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 33783982 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 10729958 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 202345530 # Number of executed instructions
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.iew.iewSquashCycles 14403927 # Number of cycles IEW is squashing
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iew.iewUnblockCycles 103 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
|
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked
|
|
|
|
|
system.cpu.iew.lsq.thread.0.forwLoads 638748 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 2434 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 295230 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 7520997 # Number of loads squashed
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.iew.lsq.thread.0.squashedStores 2461721 # Number of stores squashed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iew.memOrderViolationEvents 295230 # Number of memory order violations
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 1407484 # Number of branches that were predicted not taken incorrectly
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iew.predictedTakenIncorrect 11669168 # Number of branches that were predicted taken incorrectly
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.int_regfile_reads 457778046 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 195349960 # number of integer regfile writes
|
|
|
|
|
system.cpu.ipc 0.616718 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 0.616718 # IPC: Total IPC of All Threads
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntAlu 163185983 76.59% 76.59% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntMult 907348 0.43% 77.01% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 77.01% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 77.01% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 77.01% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 77.01% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 77.01% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 77.01% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 77.01% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 16007 0.01% 77.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 77.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 77.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 77.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 77.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 77.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 77.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 77.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 77.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 77.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 77.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 33154 0.02% 77.03% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 77.03% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 157340 0.07% 77.11% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 265597 0.12% 77.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 74720 0.04% 77.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 439795 0.21% 77.47% # Type of FU issued
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 197622 0.09% 77.57% # Type of FU issued
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 71713 0.03% 77.60% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 318 0.00% 77.60% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::MemRead 34601052 16.24% 93.84% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::MemWrite 13124839 6.16% 100.00% # Type of FU issued
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::total 213075488 # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 1172568 # FU busy when requested
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.005503 # FU busy rate (busy events/executed inst)
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.iq.ISSUE:fu_full::IntAlu 3 0.00% 0.00% # attempts to use FU when none available
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::MemRead 789273 67.31% 67.31% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::MemWrite 383292 32.69% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::samples 299565972 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.711281 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::stdev 0.810682 # Number of insts issued each cycle
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::0 130442943 43.54% 43.54% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::1 140707808 46.97% 90.51% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::2 18780101 6.27% 96.78% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::3 5513171 1.84% 98.62% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::4 2752255 0.92% 99.54% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::5 1032616 0.34% 99.89% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::6 286376 0.10% 99.98% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::7 28007 0.01% 99.99% # Number of insts issued each cycle
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::8 22695 0.01% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::total 299565972 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:rate 0.711109 # Inst issue rate
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu.iq.fp_alu_accesses 1965612 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 3923910 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 1824312 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 2255873 # Number of floating instruction queue writes
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.iq.int_alu_accesses 212282444 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 723212864 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 197607824 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 240197118 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.iqInstsAdded 219954563 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqInstsIssued 213075488 # Number of instructions issued
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 1668755 # Number of non-speculative instructions added to the IQ
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.iq.iqSquashedInstsExamined 20589653 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 247258 # Number of squashed instructions issued
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 98802 # Number of squashed non-spec instructions that were removed
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 37700924 # Number of squashed operands that are examined and possibly removed from graph
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
|
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
|
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
|
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
|
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
|
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
|
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
|
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
|
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
|
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses 1093 # number of ReadExReq accesses(hits+misses)
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34263.133641 # average ReadExReq miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31130.875576 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits 8 # number of ReadExReq hits
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 37175500 # number of ReadExReq miss cycles
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.992681 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 1085 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 33777000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.992681 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 1085 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 3921 # number of ReadReq accesses(hits+misses)
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34264.419330 # average ReadReq miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.500393 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 1355 # number of ReadReq hits
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 87922500 # number of ReadReq miss cycles
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.654425 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 2566 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits 20 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 79133500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.649324 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 2546 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 17 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 17 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_refs 0.530333 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.l2cache.demand_accesses 5014 # number of demand (read+write) accesses
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34264.037250 # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31096.254475 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_hits 1363 # number of demand (read+write) hits
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.l2cache.demand_miss_latency 125098000 # number of demand (read+write) miss cycles
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.demand_miss_rate 0.728161 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_misses 3651 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits 20 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 112910500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.724172 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 3631 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.l2cache.occ_%::0 0.055506 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_%::1 0.000152 # Average percentage of cache occupancy
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.l2cache.occ_blocks::0 1818.805056 # Average occupied blocks per context
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.occ_blocks::1 4.996217 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.overall_accesses 5014 # number of overall (read+write) accesses
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34264.037250 # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31096.254475 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.overall_hits 1363 # number of overall hits
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.l2cache.overall_miss_latency 125098000 # number of overall miss cycles
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.overall_miss_rate 0.728161 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_misses 3651 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 20 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 112910500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.724172 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 3631 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
|
|
|
system.cpu.l2cache.sampled_refs 2555 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.l2cache.tagsinuse 1823.801274 # Cycle average of tags in use
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.total_refs 1355 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
|
|
|
|
system.cpu.memDep0.conflictingLoads 3889323 # Number of conflicting loads.
|
|
|
|
|
system.cpu.memDep0.conflictingStores 2640936 # Number of conflicting stores.
|
|
|
|
|
system.cpu.memDep0.insertedLoads 37075609 # Number of loads inserted to the mem dependence unit.
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.memDep0.insertedStores 14988549 # Number of stores inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.misc_regfile_reads 328971277 # number of misc regfile reads
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu.misc_regfile_writes 4891827 # number of misc regfile writes
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.numCycles 299638429 # number of cpu cycles simulated
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
|
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.rename.RENAME:BlockCycles 3074 # Number of cycles rename is blocking
|
|
|
|
|
system.cpu.rename.RENAME:CommittedMaps 178683528 # Number of HB maps that are committed
|
|
|
|
|
system.cpu.rename.RENAME:IQFullEvents 2322 # Number of times rename has blocked due to IQ full
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.rename.RENAME:IdleCycles 73277569 # Number of cycles rename is idle
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.rename.RENAME:LSQFullEvents 19202 # Number of times rename has blocked due to LSQ full
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.rename.RENAME:RenameLookups 601039980 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.RENAME:RenamedInsts 249997488 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.RENAME:RenamedOperands 249829289 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RENAME:RunCycles 190277920 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.RENAME:SquashCycles 14403927 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.RENAME:UnblockCycles 1750037 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.RENAME:UndoneMaps 71145759 # Number of HB maps that are undone due to squashing
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu.rename.RENAME:fp_rename_lookups 14827185 # Number of floating rename lookups
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.rename.RENAME:int_rename_lookups 586212795 # Number of integer rename lookups
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.rename.RENAME:serializeStallCycles 19853445 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.RENAME:serializingInsts 2086015 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.RENAME:skidInsts 2928694 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.rename.RENAME:tempSerializingInsts 1863087 # count of temporary serializing insts renamed
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.rob.rob_reads 506290895 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 457856720 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 1374 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.workload.PROG:num_syscalls 400 # Number of system calls
|
|
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
