2004-11-13 23:10:48 +01:00
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/*
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2005-06-05 11:16:00 +02:00
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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2004-11-13 23:10:48 +01:00
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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2006-06-01 01:26:56 +02:00
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*
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* Authors: Nathan Binkert
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2004-11-13 23:10:48 +01:00
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*/
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#include <deque>
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2006-04-25 01:31:50 +02:00
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#include <limits>
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2004-11-13 23:10:48 +01:00
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#include <string>
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#include "base/inet.hh"
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2006-06-06 23:32:21 +02:00
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#include "cpu/thread_context.hh"
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2004-11-13 23:10:48 +01:00
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#include "cpu/intr_control.hh"
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#include "dev/etherlink.hh"
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#include "dev/sinic.hh"
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2006-04-25 01:31:50 +02:00
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#include "mem/packet.hh"
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2006-10-20 08:38:45 +02:00
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#include "mem/packet_access.hh"
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2004-11-13 23:10:48 +01:00
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#include "sim/builder.hh"
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#include "sim/debug.hh"
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#include "sim/eventq.hh"
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#include "sim/host.hh"
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2004-11-14 03:13:25 +01:00
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#include "sim/stats.hh"
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2006-02-27 11:35:43 +01:00
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#include "arch/vtophys.hh"
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2004-11-13 23:10:48 +01:00
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using namespace Net;
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Changes to untemplate StaticInst and StaticInstPtr, change the isa to a namespace instead of a class, an improvement to the architecture specific header file selection system, and fixed up a few include paths.
arch/alpha/alpha_linux_process.cc:
Added using directive for AlphaISA namespace
arch/alpha/alpha_memory.hh:
arch/alpha/isa/branch.isa:
cpu/pc_event.hh:
Added typedefs for Addr
arch/alpha/alpha_tru64_process.cc:
arch/alpha/arguments.cc:
Added using directive for AlphaISA
arch/alpha/ev5.hh:
Added an include of arch/alpha/isa_traits.hh, and a using directive for the AlphaISA namespace.
arch/alpha/faults.hh:
Added a typedef for the Addr type, and changed the formatting of the faults slightly.
arch/alpha/isa/main.isa:
Untemplatized StaticInst, added a using for namespace AlphaISA to show up in decoder.cc and the exec.ccs, relocated makeNop to decoder.hh
arch/alpha/isa/mem.isa:
Untemplatized StaticInst and StaticInstPtr
arch/alpha/isa/pal.isa:
cpu/base_dyn_inst.cc:
Untemplatized StaticInstPtr
arch/alpha/isa_traits.hh:
Changed variables to be externs instead of static since they are part of a namespace and not a class.
arch/alpha/stacktrace.cc:
Untemplatized StaticInstPtr, and added a using directive for AlphaISA.
arch/alpha/stacktrace.hh:
Added some typedefs for Addr and MachInst, and untemplatized StaticInstPtr
arch/alpha/vtophys.cc:
Added a using directive for AlphaISA
arch/alpha/vtophys.hh:
Added the AlphaISA namespace specifier where needed
arch/isa_parser.py:
Changed the placement of the definition of the decodeInst function to be outside the namespaceInst namespace.
base/loader/object_file.hh:
cpu/o3/bpred_unit.hh:
Added a typedef for Addr
base/loader/symtab.hh:
Added a typedef for Addr, and added a TheISA to Addr in another typedef
base/remote_gdb.cc:
Added a using namespace TheISA, and untemplatized StaticInstPtr
base/remote_gdb.hh:
Added typedefs for Addr and MachInst
cpu/base.cc:
Added TheISA specifier to some variables exported from the isa.
cpu/base.hh:
Added a typedef for Addr, and TheISA to some variables from the ISA
cpu/base_dyn_inst.hh:
Untemplatized StaticInstPtr, and added TheISA specifier to some variables from the ISA.
cpu/exec_context.hh:
Added some typedefs for types from the isa, and added TheISA specifier to some variables from the isa
cpu/exetrace.hh:
Added typedefs for some types from the ISA, and untemplatized StaticInstPtr
cpu/memtest/memtest.cc:
cpu/o3/btb.cc:
dev/baddev.cc:
dev/ide_ctrl.cc:
dev/ide_disk.cc:
dev/isa_fake.cc:
dev/ns_gige.cc:
dev/pciconfigall.cc:
dev/platform.cc:
dev/sinic.cc:
dev/uart8250.cc:
kern/freebsd/freebsd_system.cc:
kern/linux/linux_system.cc:
kern/system_events.cc:
kern/tru64/dump_mbuf.cc:
kern/tru64/tru64_events.cc:
sim/process.cc:
sim/pseudo_inst.cc:
sim/system.cc:
Added using namespace TheISA
cpu/memtest/memtest.hh:
cpu/trace/opt_cpu.hh:
cpu/trace/reader/itx_reader.hh:
dev/ide_disk.hh:
dev/pcidev.hh:
dev/platform.hh:
dev/tsunami.hh:
sim/system.hh:
sim/vptr.hh:
Added typedef for Addr
cpu/o3/2bit_local_pred.hh:
Changed the include to use arch/isa_traits.hh instead of arch/alpha/isa_traits.hh. Added typedef for Addr
cpu/o3/alpha_cpu.hh:
Added typedefs for Addr and IntReg
cpu/o3/alpha_cpu_impl.hh:
Added this-> to setNextPC to fix a problem since it didn't depend on template parameters any more. Removed "typename" where it was no longer needed.
cpu/o3/alpha_dyn_inst.hh:
Cleaned up some typedefs, and untemplatized StaticInst
cpu/o3/alpha_dyn_inst_impl.hh:
untemplatized StaticInstPtr
cpu/o3/alpha_impl.hh:
Fixed up a typedef of MachInst
cpu/o3/bpred_unit_impl.hh:
Added a using TheISA::MachInst to a function
cpu/o3/btb.hh:
Changed an include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr
cpu/o3/commit.hh:
Removed a typedef of Impl::ISA as ISA, since TheISA takes care of this now.
cpu/o3/cpu.cc:
Cleaned up namespace issues
cpu/o3/cpu.hh:
Cleaned up namespace usage
cpu/o3/decode.hh:
Removed typedef of ISA, and changed it to TheISA
cpu/o3/fetch.hh:
Fized up typedefs, and changed ISA to TheISA
cpu/o3/free_list.hh:
Changed include of arch/alpha/isa_traits.hh to arch/isa_traits.hh
cpu/o3/iew.hh:
Removed typedef of ISA
cpu/o3/iew_impl.hh:
Added TheISA namespace specifier to MachInst
cpu/o3/ras.hh:
Changed include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr.
cpu/o3/regfile.hh:
Changed ISA to TheISA, and added some typedefs for Addr, IntReg, FloatReg, and MiscRegFile
cpu/o3/rename.hh:
Changed ISA to TheISA, and added a typedef for RegIndex
cpu/o3/rename_map.hh:
Added an include for arch/isa_traits.hh, and a typedef for RegIndex
cpu/o3/rob.hh:
Added a typedef for RegIndex
cpu/o3/store_set.hh:
cpu/o3/tournament_pred.hh:
Changed an include of arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef of Addr
cpu/ozone/cpu.hh:
Changed ISA into TheISA, and untemplatized StaticInst
cpu/pc_event.cc:
Added namespace specifier TheISA to Addr types
cpu/profile.hh:
kern/kernel_stats.hh:
Added typedef for Addr, and untemplatized StaticInstPtr
cpu/simple/cpu.cc:
Changed using directive from LittleEndianGuest to AlphaISA, which will contain both namespaces. Added TheISA where needed, and untemplatized StaticInst
cpu/simple/cpu.hh:
Added a typedef for MachInst, and untemplatized StaticInst
cpu/static_inst.cc:
Untemplatized StaticInst
cpu/static_inst.hh:
Untemplatized StaticInst by using the TheISA namespace
dev/alpha_console.cc:
Added using namespace AlphaISA
dev/simple_disk.hh:
Added typedef for Addr and fixed up some formatting
dev/sinicreg.hh:
Added TheISA namespace specifier where needed
dev/tsunami.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
Added using namespace TheISA. It might be better for it to be AlphaISA
dev/tsunami_cchip.cc:
Added typedef for TheISA. It might be better for it to be AlphaISA
kern/linux/aligned.hh:
sim/pseudo_inst.hh:
Added TheISA namespace specifier to Addr
kern/linux/linux_threadinfo.hh:
Added typedef for Addr, and TheISA namespace specifier to StackPointerReg
kern/tru64/mbuf.hh:
Added TheISA to Addr type in structs
sim/process.hh:
Added typedefs of Addr, RegFile, and MachInst
sim/syscall_emul.cc:
Added using namespace TheISA, and a cast of VMPageSize to the int type
sim/syscall_emul.hh:
Added typecast for Addr, and TheISA namespace specifier for where needed
--HG--
extra : convert_revision : 91d4f6ca33a73b21c1f1771d74bfdea3b80eff45
2006-02-19 08:34:37 +01:00
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using namespace TheISA;
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2004-11-13 23:10:48 +01:00
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namespace Sinic {
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const char *RxStateStrings[] =
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{
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"rxIdle",
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"rxFifoBlock",
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"rxBeginCopy",
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"rxCopy",
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"rxCopyDone"
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};
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const char *TxStateStrings[] =
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{
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"txIdle",
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"txFifoBlock",
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"txBeginCopy",
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"txCopy",
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"txCopyDone"
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};
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///////////////////////////////////////////////////////////////////////
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//
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// Sinic PCI Device
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//
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Base::Base(Params *p)
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2005-10-19 04:05:05 +02:00
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: PciDev(p), rxEnable(false), txEnable(false), clock(p->clock),
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Make the notion of a global event tick independent of the actual
CPU cycle ticks. This allows the user to have CPUs of different
frequencies, and also allows frequencies and latencies that are
not evenly divisible by the CPU frequency. For now, the CPU
frequency is still set to the global frequency, but soon, we'll
hopefully make the global frequency fixed at something like 1THz
and set all other frequencies independently.
arch/alpha/ev5.cc:
The cycles counter is based on the current cpu cycle.
cpu/base_cpu.cc:
frequency isn't the cpu parameter anymore, cycleTime is.
cpu/base_cpu.hh:
frequency isn't the cpu parameter anymore, cycleTime is.
create several public functions for getting the cpu frequency
and the numbers of ticks for a given number of cycles, etc.
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/trace/trace_cpu.cc:
Now that ticks aren't cpu cycles, fixup code to advance
by the proper number of ticks.
cpu/memtest/memtest.hh:
cpu/trace/trace_cpu.hh:
Provide a function to get the number of ticks for a given
number of cycles.
dev/alpha_console.cc:
Update for changes in the way that frequencies and latencies are
accessed. Move some stuff to init()
dev/alpha_console.hh:
Need a pointer to the system and the cpu to get the frequency
so we can pass the info to the console code.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
dev/ide_disk.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
Add some extra debugging printfs
dev/platform.cc:
dev/sinic.cc:
dev/sinic.hh:
outline the constructor and destructor
dev/platform.hh:
outline the constructor and destructor.
don't keep track of the interrupt frequency. Only provide the
accessor function.
dev/tsunami.cc:
dev/tsunami.hh:
outline the constructor and destructor
Don't set the interrupt frequency here. Get it from the actual device
that does the interrupting.
dev/tsunami_io.cc:
dev/tsunami_io.hh:
Make the interrupt interval a configuration parameter. (And convert
the interval to the new latency/frequency stuff in the python)
kern/linux/linux_system.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
kern/tru64/tru64_system.cc:
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
python/m5/config.py:
Fix support for cycle_time relative latencies and frequencies.
Add support for getting a NetworkBandwidth or a MemoryBandwidth.
python/m5/objects/BaseCPU.mpy:
All CPUs now have a cycle_time. The default is the global frequency,
but it is now possible to set the global frequency to some large value
(like 1THz) and set each CPU frequency independently.
python/m5/objects/BaseCache.mpy:
python/m5/objects/Ide.mpy:
Make this a Latency parameter
python/m5/objects/BaseSystem.mpy:
We need to pass the boot CPU's frequency to the system
python/m5/objects/Ethernet.mpy:
Update parameter types to use latency and bandwidth types
python/m5/objects/Platform.mpy:
this frequency isn't needed. We get it from the clock interrupt.
python/m5/objects/Tsunami.mpy:
The clock generator should hold the frequency
sim/eventq.hh:
Need to remove this assertion because the writeback event
queue is different from the CPU's event queue which can cause
this assertion to fail.
sim/process.cc:
Fix comment.
sim/system.hh:
Struct member to hold the boot CPU's frequency.
sim/universe.cc:
remove unneeded variable.
--HG--
extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
2005-04-11 21:32:06 +02:00
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intrDelay(p->intr_delay), intrTick(0), cpuIntrEnable(false),
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cpuPendingIntr(false), intrEvent(0), interface(NULL)
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2004-11-13 23:10:48 +01:00
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{
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}
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Device::Device(Params *p)
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2006-05-18 18:52:16 +02:00
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: Base(p), rxUnique(0), txUnique(0),
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2006-04-26 23:52:33 +02:00
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virtualRegs(p->virtual_count < 1 ? 1 : p->virtual_count),
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2006-05-18 18:52:16 +02:00
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rxFifo(p->rx_fifo_size), txFifo(p->tx_fifo_size),
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2004-11-13 23:10:48 +01:00
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rxKickTick(0), txKickTick(0),
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txEvent(this), rxDmaEvent(this), txDmaEvent(this),
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dmaReadDelay(p->dma_read_delay), dmaReadFactor(p->dma_read_factor),
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dmaWriteDelay(p->dma_write_delay), dmaWriteFactor(p->dma_write_factor)
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{
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reset();
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}
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Device::~Device()
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{}
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void
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Device::regStats()
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{
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rxBytes
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.name(name() + ".rxBytes")
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.desc("Bytes Received")
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.prereq(rxBytes)
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;
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rxBandwidth
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.name(name() + ".rxBandwidth")
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.desc("Receive Bandwidth (bits/s)")
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.precision(0)
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.prereq(rxBytes)
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;
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rxPackets
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.name(name() + ".rxPackets")
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.desc("Number of Packets Received")
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.prereq(rxBytes)
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;
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rxPacketRate
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.name(name() + ".rxPPS")
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.desc("Packet Reception Rate (packets/s)")
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.precision(0)
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.prereq(rxBytes)
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;
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rxIpPackets
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.name(name() + ".rxIpPackets")
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.desc("Number of IP Packets Received")
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.prereq(rxBytes)
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;
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rxTcpPackets
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.name(name() + ".rxTcpPackets")
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.desc("Number of Packets Received")
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.prereq(rxBytes)
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;
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rxUdpPackets
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.name(name() + ".rxUdpPackets")
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.desc("Number of UDP Packets Received")
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.prereq(rxBytes)
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;
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rxIpChecksums
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.name(name() + ".rxIpChecksums")
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.desc("Number of rx IP Checksums done by device")
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.precision(0)
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.prereq(rxBytes)
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;
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rxTcpChecksums
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.name(name() + ".rxTcpChecksums")
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.desc("Number of rx TCP Checksums done by device")
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.precision(0)
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.prereq(rxBytes)
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;
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rxUdpChecksums
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.name(name() + ".rxUdpChecksums")
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.desc("Number of rx UDP Checksums done by device")
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.precision(0)
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.prereq(rxBytes)
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;
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2005-01-20 00:40:02 +01:00
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totBandwidth
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.name(name() + ".totBandwidth")
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.desc("Total Bandwidth (bits/s)")
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.precision(0)
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.prereq(totBytes)
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;
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totPackets
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.name(name() + ".totPackets")
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.desc("Total Packets")
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.precision(0)
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.prereq(totBytes)
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;
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|
|
|
totBytes
|
|
|
|
|
.name(name() + ".totBytes")
|
|
|
|
|
.desc("Total Bytes")
|
|
|
|
|
.precision(0)
|
|
|
|
|
.prereq(totBytes)
|
|
|
|
|
;
|
|
|
|
|
|
|
|
|
|
totPacketRate
|
|
|
|
|
.name(name() + ".totPPS")
|
|
|
|
|
.desc("Total Tranmission Rate (packets/s)")
|
|
|
|
|
.precision(0)
|
|
|
|
|
.prereq(totBytes)
|
|
|
|
|
;
|
|
|
|
|
|
2004-11-13 23:10:48 +01:00
|
|
|
txBytes
|
|
|
|
|
.name(name() + ".txBytes")
|
|
|
|
|
.desc("Bytes Transmitted")
|
|
|
|
|
.prereq(txBytes)
|
|
|
|
|
;
|
|
|
|
|
|
|
|
|
|
txBandwidth
|
|
|
|
|
.name(name() + ".txBandwidth")
|
|
|
|
|
.desc("Transmit Bandwidth (bits/s)")
|
|
|
|
|
.precision(0)
|
|
|
|
|
.prereq(txBytes)
|
|
|
|
|
;
|
|
|
|
|
|
|
|
|
|
txPackets
|
|
|
|
|
.name(name() + ".txPackets")
|
|
|
|
|
.desc("Number of Packets Transmitted")
|
|
|
|
|
.prereq(txBytes)
|
|
|
|
|
;
|
|
|
|
|
|
|
|
|
|
txPacketRate
|
|
|
|
|
.name(name() + ".txPPS")
|
|
|
|
|
.desc("Packet Tranmission Rate (packets/s)")
|
|
|
|
|
.precision(0)
|
|
|
|
|
.prereq(txBytes)
|
|
|
|
|
;
|
|
|
|
|
|
|
|
|
|
txIpPackets
|
|
|
|
|
.name(name() + ".txIpPackets")
|
|
|
|
|
.desc("Number of IP Packets Transmitted")
|
|
|
|
|
.prereq(txBytes)
|
|
|
|
|
;
|
|
|
|
|
|
|
|
|
|
txTcpPackets
|
|
|
|
|
.name(name() + ".txTcpPackets")
|
|
|
|
|
.desc("Number of TCP Packets Transmitted")
|
|
|
|
|
.prereq(txBytes)
|
|
|
|
|
;
|
|
|
|
|
|
|
|
|
|
txUdpPackets
|
|
|
|
|
.name(name() + ".txUdpPackets")
|
|
|
|
|
.desc("Number of Packets Transmitted")
|
|
|
|
|
.prereq(txBytes)
|
|
|
|
|
;
|
|
|
|
|
|
|
|
|
|
txIpChecksums
|
|
|
|
|
.name(name() + ".txIpChecksums")
|
|
|
|
|
.desc("Number of tx IP Checksums done by device")
|
|
|
|
|
.precision(0)
|
|
|
|
|
.prereq(txBytes)
|
|
|
|
|
;
|
|
|
|
|
|
|
|
|
|
txTcpChecksums
|
|
|
|
|
.name(name() + ".txTcpChecksums")
|
|
|
|
|
.desc("Number of tx TCP Checksums done by device")
|
|
|
|
|
.precision(0)
|
|
|
|
|
.prereq(txBytes)
|
|
|
|
|
;
|
|
|
|
|
|
|
|
|
|
txUdpChecksums
|
|
|
|
|
.name(name() + ".txUdpChecksums")
|
|
|
|
|
.desc("Number of tx UDP Checksums done by device")
|
|
|
|
|
.precision(0)
|
|
|
|
|
.prereq(txBytes)
|
|
|
|
|
;
|
|
|
|
|
|
|
|
|
|
txBandwidth = txBytes * Stats::constant(8) / simSeconds;
|
|
|
|
|
rxBandwidth = rxBytes * Stats::constant(8) / simSeconds;
|
2005-01-20 00:40:02 +01:00
|
|
|
totBandwidth = txBandwidth + rxBandwidth;
|
|
|
|
|
totBytes = txBytes + rxBytes;
|
|
|
|
|
totPackets = txPackets + rxPackets;
|
2004-11-13 23:10:48 +01:00
|
|
|
txPacketRate = txPackets / simSeconds;
|
|
|
|
|
rxPacketRate = rxPackets / simSeconds;
|
|
|
|
|
}
|
|
|
|
|
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
void
|
2005-11-25 19:33:36 +01:00
|
|
|
Device::prepareIO(int cpu, int index)
|
2005-11-22 05:43:15 +01:00
|
|
|
{
|
2005-11-25 19:33:36 +01:00
|
|
|
int size = virtualRegs.size();
|
2006-04-26 23:52:33 +02:00
|
|
|
if (index > size)
|
|
|
|
|
panic("Trying to access a vnic that doesn't exist %d > %d\n",
|
|
|
|
|
index, size);
|
2005-11-22 05:43:15 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
2005-11-25 19:33:36 +01:00
|
|
|
Device::prepareRead(int cpu, int index)
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
{
|
|
|
|
|
using namespace Regs;
|
2005-11-25 19:33:36 +01:00
|
|
|
prepareIO(cpu, index);
|
|
|
|
|
|
|
|
|
|
VirtualReg &vnic = virtualRegs[index];
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
|
|
|
|
|
// update rx registers
|
2005-11-25 19:33:36 +01:00
|
|
|
uint64_t rxdone = vnic.RxDone;
|
2006-04-26 23:52:33 +02:00
|
|
|
rxdone = set_RxDone_Packets(rxdone, rxFifo.countPacketsAfter(rxFifoPtr));
|
|
|
|
|
rxdone = set_RxDone_Empty(rxdone, rxFifo.empty());
|
|
|
|
|
rxdone = set_RxDone_High(rxdone, rxFifo.size() > regs.RxFifoMark);
|
|
|
|
|
rxdone = set_RxDone_NotHigh(rxdone, rxLow);
|
2005-11-25 19:33:36 +01:00
|
|
|
regs.RxData = vnic.RxData;
|
|
|
|
|
regs.RxDone = rxdone;
|
|
|
|
|
regs.RxWait = rxdone;
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
|
|
|
|
|
// update tx regsiters
|
2005-11-25 19:33:36 +01:00
|
|
|
uint64_t txdone = vnic.TxDone;
|
|
|
|
|
txdone = set_TxDone_Packets(txdone, txFifo.packets());
|
|
|
|
|
txdone = set_TxDone_Full(txdone, txFifo.avail() < regs.TxMaxCopy);
|
|
|
|
|
txdone = set_TxDone_Low(txdone, txFifo.size() < regs.TxFifoMark);
|
|
|
|
|
regs.TxData = vnic.TxData;
|
|
|
|
|
regs.TxDone = txdone;
|
|
|
|
|
regs.TxWait = txdone;
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
}
|
|
|
|
|
|
2005-11-22 05:43:15 +01:00
|
|
|
void
|
2005-11-25 19:33:36 +01:00
|
|
|
Device::prepareWrite(int cpu, int index)
|
2005-11-22 05:43:15 +01:00
|
|
|
{
|
2005-11-25 19:33:36 +01:00
|
|
|
prepareIO(cpu, index);
|
2005-11-22 05:43:15 +01:00
|
|
|
}
|
|
|
|
|
|
2004-11-13 23:10:48 +01:00
|
|
|
/**
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
* I/O read of device register
|
2004-11-13 23:10:48 +01:00
|
|
|
*/
|
2006-04-25 01:31:50 +02:00
|
|
|
Tick
|
2006-10-20 09:10:12 +02:00
|
|
|
Device::read(PacketPtr pkt)
|
2004-11-13 23:10:48 +01:00
|
|
|
{
|
2005-08-15 22:59:58 +02:00
|
|
|
assert(config.command & PCI_CMD_MSE);
|
2006-05-26 20:17:33 +02:00
|
|
|
assert(pkt->getAddr() >= BARAddrs[0] && pkt->getSize() < BARSize[0]);
|
2005-11-22 03:52:04 +01:00
|
|
|
|
2006-05-19 04:32:21 +02:00
|
|
|
int cpu = pkt->req->getCpuNum();
|
2006-05-26 20:17:33 +02:00
|
|
|
Addr daddr = pkt->getAddr() - BARAddrs[0];
|
2005-11-25 19:33:36 +01:00
|
|
|
Addr index = daddr >> Regs::VirtualShift;
|
|
|
|
|
Addr raddr = daddr & Regs::VirtualMask;
|
2005-11-22 05:43:15 +01:00
|
|
|
|
2006-05-19 04:32:21 +02:00
|
|
|
pkt->allocate();
|
2006-04-25 01:31:50 +02:00
|
|
|
|
2005-11-25 19:33:36 +01:00
|
|
|
if (!regValid(raddr))
|
2006-05-13 00:16:07 +02:00
|
|
|
panic("invalid register: cpu=%d vnic=%d da=%#x pa=%#x size=%d",
|
2006-05-26 20:17:33 +02:00
|
|
|
cpu, index, daddr, pkt->getAddr(), pkt->getSize());
|
2004-11-13 23:10:48 +01:00
|
|
|
|
2005-11-25 19:33:36 +01:00
|
|
|
const Regs::Info &info = regInfo(raddr);
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
if (!info.read)
|
2006-04-25 16:40:35 +02:00
|
|
|
panic("read %s (write only): "
|
2006-05-13 00:16:07 +02:00
|
|
|
"cpu=%d vnic=%d da=%#x pa=%#x size=%d",
|
2006-05-26 20:17:33 +02:00
|
|
|
info.name, cpu, index, daddr, pkt->getAddr(), pkt->getSize());
|
2004-11-13 23:10:48 +01:00
|
|
|
|
2006-04-25 16:40:35 +02:00
|
|
|
panic("read %s (invalid size): "
|
2006-05-13 00:16:07 +02:00
|
|
|
"cpu=%d vnic=%d da=%#x pa=%#x size=%d",
|
2006-05-26 20:17:33 +02:00
|
|
|
info.name, cpu, index, daddr, pkt->getAddr(), pkt->getSize());
|
2004-11-13 23:10:48 +01:00
|
|
|
|
2005-11-25 19:33:36 +01:00
|
|
|
prepareRead(cpu, index);
|
2004-11-13 23:10:48 +01:00
|
|
|
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
uint64_t value = 0;
|
2006-05-26 20:17:33 +02:00
|
|
|
if (pkt->getSize() == 4) {
|
2006-04-25 01:31:50 +02:00
|
|
|
uint32_t reg = regData32(raddr);
|
2006-05-19 04:32:21 +02:00
|
|
|
pkt->set(reg);
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
value = reg;
|
|
|
|
|
}
|
2004-11-13 23:10:48 +01:00
|
|
|
|
2006-05-26 20:17:33 +02:00
|
|
|
if (pkt->getSize() == 8) {
|
2006-04-25 01:31:50 +02:00
|
|
|
uint64_t reg = regData64(raddr);
|
2006-05-19 04:32:21 +02:00
|
|
|
pkt->set(reg);
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
value = reg;
|
|
|
|
|
}
|
2004-11-13 23:10:48 +01:00
|
|
|
|
2005-11-22 06:17:05 +01:00
|
|
|
DPRINTF(EthernetPIO,
|
2006-05-13 00:16:07 +02:00
|
|
|
"read %s: cpu=%d vnic=%d da=%#x pa=%#x size=%d val=%#x\n",
|
2006-05-26 20:17:33 +02:00
|
|
|
info.name, cpu, index, daddr, pkt->getAddr(), pkt->getSize(), value);
|
2004-11-13 23:10:48 +01:00
|
|
|
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
// reading the interrupt status register has the side effect of
|
|
|
|
|
// clearing it
|
2005-11-25 19:33:36 +01:00
|
|
|
if (raddr == Regs::IntrStatus)
|
2004-11-13 23:10:48 +01:00
|
|
|
devIntrClear();
|
|
|
|
|
|
2006-04-25 01:31:50 +02:00
|
|
|
return pioDelay;
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
}
|
2004-11-13 23:10:48 +01:00
|
|
|
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
/**
|
|
|
|
|
* IPR read of device register
|
2006-04-25 01:31:50 +02:00
|
|
|
|
|
|
|
|
Fault
|
2005-11-22 05:43:15 +01:00
|
|
|
Device::iprRead(Addr daddr, int cpu, uint64_t &result)
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
{
|
|
|
|
|
if (!regValid(daddr))
|
|
|
|
|
panic("invalid address: da=%#x", daddr);
|
2004-11-13 23:10:48 +01:00
|
|
|
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
const Regs::Info &info = regInfo(daddr);
|
|
|
|
|
if (!info.read)
|
2005-11-22 06:17:05 +01:00
|
|
|
panic("reading %s (write only): cpu=%d da=%#x", info.name, cpu, daddr);
|
2004-11-13 23:10:48 +01:00
|
|
|
|
2005-11-22 06:17:05 +01:00
|
|
|
DPRINTF(EthernetPIO, "IPR read %s: cpu=%d da=%#x\n",
|
|
|
|
|
info.name, cpu, daddr);
|
2004-11-13 23:10:48 +01:00
|
|
|
|
2005-11-25 19:33:36 +01:00
|
|
|
prepareRead(cpu, 0);
|
2004-11-13 23:10:48 +01:00
|
|
|
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
if (info.size == 4)
|
|
|
|
|
result = regData32(daddr);
|
2004-11-13 23:10:48 +01:00
|
|
|
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
if (info.size == 8)
|
|
|
|
|
result = regData64(daddr);
|
2004-11-13 23:10:48 +01:00
|
|
|
|
2005-11-22 06:17:05 +01:00
|
|
|
DPRINTF(EthernetPIO, "IPR read %s: cpu=%s da=%#x val=%#x\n",
|
|
|
|
|
info.name, cpu, result);
|
2004-11-13 23:10:48 +01:00
|
|
|
|
Changed the fault enum into a class, and fixed everything up to work with it. Next, the faults need to be pulled out of all the other code so that they are only used to communicate between the CPU and the ISA.
SConscript:
The new faults.cc file in sim allocates the system wide faults. When these faults are generated through a function interface in the ISA, this file may go away.
arch/alpha/alpha_memory.cc:
Changed Fault to Fault * and took the underscores out of fault names.
arch/alpha/alpha_memory.hh:
Changed Fault to Fault *. Also, added an include for the alpha faults.
arch/alpha/ev5.cc:
Changed the fault_addr array into a fault_addr function. Once all of the faults can be expected to have the same type, fault_addr can go away completely and the info it provided will come from the fault itself. Also, Fault was changed to Fault *, and underscores were taken out of fault names.
arch/alpha/isa/decoder.isa:
Changed Fault to Fault * and took the underscores out fault names.
arch/alpha/isa/fp.isa:
Changed Fault to Fault *, and took the underscores out of fault names.
arch/alpha/isa/main.isa:
Changed Fault to Fault *, removed underscores from fault names, and made an include of the alpha faults show up in all the generated files.
arch/alpha/isa/mem.isa:
Changed Fault to Fault * and removed underscores from fault names.
arch/alpha/isa/unimp.isa:
arch/alpha/isa/unknown.isa:
cpu/exec_context.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.cc:
dev/alpha_console.cc:
dev/ide_ctrl.cc:
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/pcidev.cc:
dev/pcidev.hh:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
Changed Fault to Fault *, and removed underscores from fault names.
arch/alpha/isa_traits.hh:
Changed the include of arch/alpha/faults.hh to sim/faults.hh, since the alpha faults weren't needed.
cpu/base_dyn_inst.cc:
Changed Fault to Fault *, and removed underscores from fault names. This file probably shouldn't use the Unimplemented Opcode fault.
cpu/base_dyn_inst.hh:
Changed Fault to Fault * and took the underscores out of the fault names.
cpu/exec_context.cc:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_dyn_inst_impl.hh:
cpu/o3/fetch.hh:
dev/alpha_console.hh:
dev/baddev.hh:
dev/ide_ctrl.hh:
dev/isa_fake.hh:
dev/ns_gige.hh:
dev/pciconfigall.hh:
dev/sinic.hh:
dev/tsunami_cchip.hh:
dev/tsunami_io.hh:
dev/tsunami_pchip.hh:
dev/uart.hh:
dev/uart8250.hh:
Changed Fault to Fault *.
cpu/o3/alpha_cpu.hh:
Changed Fault to Fault *, removed underscores from fault names.
cpu/o3/alpha_cpu_impl.hh:
Changed Fault to Fault *, removed underscores from fault names, and changed the fault_addr array to the fault_addr function. Once all faults are from the ISA, this function will probably go away.
cpu/o3/commit_impl.hh:
cpu/o3/fetch_impl.hh:
dev/baddev.cc:
Changed Fault to Fault *, and removed underscores from the fault names.
cpu/o3/regfile.hh:
Added an include for the alpha specific faults which will hopefully go away once the ipr stuff is moved, changed Fault to Fault *, and removed the underscores from fault names.
cpu/simple/cpu.hh:
Changed Fault to Fault *
dev/ns_gige.cc:
Changed Fault to Fault *, and removdd underscores from fault names.
dev/sinic.cc:
Changed Fault to Fault *, and removed the underscores from fault names.
dev/uart8250.cc:
Chanted Fault to Fault *, and removed underscores from fault names.
kern/kernel_stats.cc:
Removed underscores from fault names, and from NumFaults.
kern/kernel_stats.hh:
Changed the predeclaration of Fault from an enum to a class, and changd the "fault" function to work with the classes instead of the enum. Once there are no system wide faults anymore, this code will simplify back to something like it was originally.
sim/faults.cc:
This allocates the system wide faults.
sim/faults.hh:
This declares the system wide faults.
sim/syscall_emul.cc:
sim/syscall_emul.hh:
Removed the underscores from fault names.
--HG--
rename : arch/alpha/faults.cc => sim/faults.cc
rename : arch/alpha/faults.hh => sim/faults.hh
extra : convert_revision : 253d39258237333ae8ec4d8047367cb3ea68569d
2006-02-16 07:22:51 +01:00
|
|
|
return NoFault;
|
2004-11-13 23:10:48 +01:00
|
|
|
}
|
2006-04-25 01:31:50 +02:00
|
|
|
*/
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
/**
|
|
|
|
|
* I/O write of device register
|
|
|
|
|
*/
|
2006-04-25 01:31:50 +02:00
|
|
|
Tick
|
2006-10-20 09:10:12 +02:00
|
|
|
Device::write(PacketPtr pkt)
|
2004-11-13 23:10:48 +01:00
|
|
|
{
|
2005-08-15 22:59:58 +02:00
|
|
|
assert(config.command & PCI_CMD_MSE);
|
2006-05-26 20:17:33 +02:00
|
|
|
assert(pkt->getAddr() >= BARAddrs[0] && pkt->getSize() < BARSize[0]);
|
2004-11-13 23:10:48 +01:00
|
|
|
|
2006-05-19 04:32:21 +02:00
|
|
|
int cpu = pkt->req->getCpuNum();
|
2006-05-26 20:17:33 +02:00
|
|
|
Addr daddr = pkt->getAddr() - BARAddrs[0];
|
2005-11-25 19:33:36 +01:00
|
|
|
Addr index = daddr >> Regs::VirtualShift;
|
|
|
|
|
Addr raddr = daddr & Regs::VirtualMask;
|
2005-11-22 05:43:15 +01:00
|
|
|
|
2005-11-25 19:33:36 +01:00
|
|
|
if (!regValid(raddr))
|
2006-04-25 01:31:50 +02:00
|
|
|
panic("invalid register: cpu=%d, da=%#x pa=%#x size=%d",
|
2006-05-26 20:17:33 +02:00
|
|
|
cpu, daddr, pkt->getAddr(), pkt->getSize());
|
2004-11-13 23:10:48 +01:00
|
|
|
|
2005-11-25 19:33:36 +01:00
|
|
|
const Regs::Info &info = regInfo(raddr);
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
if (!info.write)
|
2006-04-25 16:40:35 +02:00
|
|
|
panic("write %s (read only): "
|
2006-05-13 00:16:07 +02:00
|
|
|
"cpu=%d vnic=%d da=%#x pa=%#x size=%d",
|
2006-05-26 20:17:33 +02:00
|
|
|
info.name, cpu, index, daddr, pkt->getAddr(), pkt->getSize());
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
|
2006-05-26 20:17:33 +02:00
|
|
|
if (pkt->getSize() != info.size)
|
2006-04-25 16:40:35 +02:00
|
|
|
panic("write %s (invalid size): "
|
2006-05-13 00:16:07 +02:00
|
|
|
"cpu=%d vnic=%d da=%#x pa=%#x size=%d",
|
2006-05-26 20:17:33 +02:00
|
|
|
info.name, cpu, index, daddr, pkt->getAddr(), pkt->getSize());
|
2004-11-13 23:10:48 +01:00
|
|
|
|
2006-02-28 12:17:57 +01:00
|
|
|
VirtualReg &vnic = virtualRegs[index];
|
|
|
|
|
|
2005-11-22 06:17:05 +01:00
|
|
|
DPRINTF(EthernetPIO,
|
2006-05-13 00:16:07 +02:00
|
|
|
"write %s vnic %d: cpu=%d val=%#x da=%#x pa=%#x size=%d\n",
|
2006-05-19 04:32:21 +02:00
|
|
|
info.name, index, cpu, info.size == 4 ? pkt->get<uint32_t>() :
|
2006-05-26 20:17:33 +02:00
|
|
|
pkt->get<uint64_t>(), daddr, pkt->getAddr(), pkt->getSize());
|
2004-11-13 23:10:48 +01:00
|
|
|
|
2005-11-25 19:33:36 +01:00
|
|
|
prepareWrite(cpu, index);
|
2004-11-13 23:10:48 +01:00
|
|
|
|
2005-11-25 19:33:36 +01:00
|
|
|
switch (raddr) {
|
2004-11-13 23:10:48 +01:00
|
|
|
case Regs::Config:
|
2006-05-19 04:32:21 +02:00
|
|
|
changeConfig(pkt->get<uint32_t>());
|
2004-11-13 23:10:48 +01:00
|
|
|
break;
|
|
|
|
|
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
case Regs::Command:
|
2006-05-19 04:32:21 +02:00
|
|
|
command(pkt->get<uint32_t>());
|
2004-11-13 23:10:48 +01:00
|
|
|
break;
|
|
|
|
|
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
case Regs::IntrStatus:
|
2006-05-19 04:32:21 +02:00
|
|
|
devIntrClear(regs.IntrStatus & pkt->get<uint32_t>());
|
2004-11-13 23:10:48 +01:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case Regs::IntrMask:
|
2006-05-19 04:32:21 +02:00
|
|
|
devIntrChangeMask(pkt->get<uint32_t>());
|
2004-11-13 23:10:48 +01:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case Regs::RxData:
|
2005-11-25 19:33:36 +01:00
|
|
|
if (Regs::get_RxDone_Busy(vnic.RxDone))
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
panic("receive machine busy with another request! rxState=%s",
|
|
|
|
|
RxStateStrings[rxState]);
|
2004-11-13 23:10:48 +01:00
|
|
|
|
2006-04-26 23:52:33 +02:00
|
|
|
vnic.rxUnique = rxUnique++;
|
2005-11-25 19:33:36 +01:00
|
|
|
vnic.RxDone = Regs::RxDone_Busy;
|
2006-05-19 04:32:21 +02:00
|
|
|
vnic.RxData = pkt->get<uint64_t>();
|
2006-04-26 23:52:33 +02:00
|
|
|
|
2006-05-19 04:32:21 +02:00
|
|
|
if (Regs::get_RxData_Vaddr(pkt->get<uint64_t>())) {
|
2006-05-18 18:52:16 +02:00
|
|
|
panic("vtophys not implemented in newmem");
|
|
|
|
|
/* Addr vaddr = Regs::get_RxData_Addr(reg64);
|
2006-04-26 23:52:33 +02:00
|
|
|
Addr paddr = vtophys(req->xc, vaddr);
|
|
|
|
|
DPRINTF(EthernetPIO, "write RxData vnic %d (rxunique %d): "
|
|
|
|
|
"vaddr=%#x, paddr=%#x\n",
|
|
|
|
|
index, vnic.rxUnique, vaddr, paddr);
|
|
|
|
|
|
2006-05-18 18:52:16 +02:00
|
|
|
vnic.RxData = Regs::set_RxData_Addr(vnic.RxData, paddr);*/
|
2006-04-26 23:52:33 +02:00
|
|
|
} else {
|
|
|
|
|
DPRINTF(EthernetPIO, "write RxData vnic %d (rxunique %d)\n",
|
|
|
|
|
index, vnic.rxUnique);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (vnic.rxPacket == rxFifo.end()) {
|
|
|
|
|
DPRINTF(EthernetPIO, "request new packet...appending to rxList\n");
|
|
|
|
|
rxList.push_back(index);
|
|
|
|
|
} else {
|
|
|
|
|
DPRINTF(EthernetPIO, "packet exists...appending to rxBusy\n");
|
|
|
|
|
rxBusy.push_back(index);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (rxEnable && (rxState == rxIdle || rxState == rxFifoBlock)) {
|
2004-11-13 23:10:48 +01:00
|
|
|
rxState = rxFifoBlock;
|
|
|
|
|
rxKick();
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case Regs::TxData:
|
2005-11-25 19:33:36 +01:00
|
|
|
if (Regs::get_TxDone_Busy(vnic.TxDone))
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
panic("transmit machine busy with another request! txState=%s",
|
|
|
|
|
TxStateStrings[txState]);
|
2004-11-13 23:10:48 +01:00
|
|
|
|
2006-04-26 23:52:33 +02:00
|
|
|
vnic.txUnique = txUnique++;
|
2005-11-25 19:33:36 +01:00
|
|
|
vnic.TxDone = Regs::TxDone_Busy;
|
2006-04-26 23:52:33 +02:00
|
|
|
|
2006-05-19 04:32:21 +02:00
|
|
|
if (Regs::get_TxData_Vaddr(pkt->get<uint64_t>())) {
|
2006-05-13 00:16:07 +02:00
|
|
|
panic("vtophys won't work here in newmem.\n");
|
|
|
|
|
/*Addr vaddr = Regs::get_TxData_Addr(reg64);
|
2006-04-26 23:52:33 +02:00
|
|
|
Addr paddr = vtophys(req->xc, vaddr);
|
|
|
|
|
DPRINTF(EthernetPIO, "write TxData vnic %d (rxunique %d): "
|
|
|
|
|
"vaddr=%#x, paddr=%#x\n",
|
|
|
|
|
index, vnic.txUnique, vaddr, paddr);
|
|
|
|
|
|
2006-05-13 00:16:07 +02:00
|
|
|
vnic.TxData = Regs::set_TxData_Addr(vnic.TxData, paddr);*/
|
2006-04-26 23:52:33 +02:00
|
|
|
} else {
|
|
|
|
|
DPRINTF(EthernetPIO, "write TxData vnic %d (rxunique %d)\n",
|
|
|
|
|
index, vnic.txUnique);
|
|
|
|
|
}
|
|
|
|
|
|
2005-11-25 19:33:36 +01:00
|
|
|
if (txList.empty() || txList.front() != index)
|
|
|
|
|
txList.push_back(index);
|
2005-11-29 00:40:58 +01:00
|
|
|
if (txEnable && txState == txIdle && txList.front() == index) {
|
2004-11-13 23:10:48 +01:00
|
|
|
txState = txFifoBlock;
|
|
|
|
|
txKick();
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
2006-02-28 12:17:57 +01:00
|
|
|
|
2006-04-25 01:31:50 +02:00
|
|
|
return pioDelay;
|
2004-11-13 23:10:48 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
Device::devIntrPost(uint32_t interrupts)
|
|
|
|
|
{
|
|
|
|
|
if ((interrupts & Regs::Intr_Res))
|
|
|
|
|
panic("Cannot set a reserved interrupt");
|
|
|
|
|
|
|
|
|
|
regs.IntrStatus |= interrupts;
|
|
|
|
|
|
|
|
|
|
DPRINTF(EthernetIntr,
|
|
|
|
|
"interrupt written to intStatus: intr=%#x status=%#x mask=%#x\n",
|
|
|
|
|
interrupts, regs.IntrStatus, regs.IntrMask);
|
|
|
|
|
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
interrupts = regs.IntrStatus & regs.IntrMask;
|
|
|
|
|
|
|
|
|
|
// Intr_RxHigh is special, we only signal it if we've emptied the fifo
|
|
|
|
|
// and then filled it above the high watermark
|
|
|
|
|
if (rxEmpty)
|
|
|
|
|
rxEmpty = false;
|
|
|
|
|
else
|
|
|
|
|
interrupts &= ~Regs::Intr_RxHigh;
|
|
|
|
|
|
|
|
|
|
// Intr_TxLow is special, we only signal it if we've filled up the fifo
|
|
|
|
|
// and then dropped below the low watermark
|
|
|
|
|
if (txFull)
|
|
|
|
|
txFull = false;
|
|
|
|
|
else
|
|
|
|
|
interrupts &= ~Regs::Intr_TxLow;
|
|
|
|
|
|
|
|
|
|
if (interrupts) {
|
2004-11-13 23:10:48 +01:00
|
|
|
Tick when = curTick;
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
if ((interrupts & Regs::Intr_NoDelay) == 0)
|
2004-11-13 23:10:48 +01:00
|
|
|
when += intrDelay;
|
|
|
|
|
cpuIntrPost(when);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
Device::devIntrClear(uint32_t interrupts)
|
|
|
|
|
{
|
|
|
|
|
if ((interrupts & Regs::Intr_Res))
|
|
|
|
|
panic("Cannot clear a reserved interrupt");
|
|
|
|
|
|
|
|
|
|
regs.IntrStatus &= ~interrupts;
|
|
|
|
|
|
|
|
|
|
DPRINTF(EthernetIntr,
|
|
|
|
|
"interrupt cleared from intStatus: intr=%x status=%x mask=%x\n",
|
|
|
|
|
interrupts, regs.IntrStatus, regs.IntrMask);
|
|
|
|
|
|
|
|
|
|
if (!(regs.IntrStatus & regs.IntrMask))
|
|
|
|
|
cpuIntrClear();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
Device::devIntrChangeMask(uint32_t newmask)
|
|
|
|
|
{
|
|
|
|
|
if (regs.IntrMask == newmask)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
regs.IntrMask = newmask;
|
|
|
|
|
|
|
|
|
|
DPRINTF(EthernetIntr,
|
|
|
|
|
"interrupt mask changed: intStatus=%x intMask=%x masked=%x\n",
|
|
|
|
|
regs.IntrStatus, regs.IntrMask, regs.IntrStatus & regs.IntrMask);
|
|
|
|
|
|
|
|
|
|
if (regs.IntrStatus & regs.IntrMask)
|
|
|
|
|
cpuIntrPost(curTick);
|
|
|
|
|
else
|
|
|
|
|
cpuIntrClear();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
Base::cpuIntrPost(Tick when)
|
|
|
|
|
{
|
|
|
|
|
// If the interrupt you want to post is later than an interrupt
|
|
|
|
|
// already scheduled, just let it post in the coming one and don't
|
|
|
|
|
// schedule another.
|
|
|
|
|
// HOWEVER, must be sure that the scheduled intrTick is in the
|
|
|
|
|
// future (this was formerly the source of a bug)
|
|
|
|
|
/**
|
|
|
|
|
* @todo this warning should be removed and the intrTick code should
|
|
|
|
|
* be fixed.
|
|
|
|
|
*/
|
|
|
|
|
assert(when >= curTick);
|
|
|
|
|
assert(intrTick >= curTick || intrTick == 0);
|
|
|
|
|
if (!cpuIntrEnable) {
|
|
|
|
|
DPRINTF(EthernetIntr, "interrupts not enabled.\n",
|
|
|
|
|
intrTick);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (when > intrTick && intrTick != 0) {
|
|
|
|
|
DPRINTF(EthernetIntr, "don't need to schedule event...intrTick=%d\n",
|
|
|
|
|
intrTick);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
intrTick = when;
|
|
|
|
|
if (intrTick < curTick) {
|
|
|
|
|
debug_break();
|
|
|
|
|
intrTick = curTick;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
DPRINTF(EthernetIntr, "going to schedule an interrupt for intrTick=%d\n",
|
|
|
|
|
intrTick);
|
|
|
|
|
|
|
|
|
|
if (intrEvent)
|
|
|
|
|
intrEvent->squash();
|
|
|
|
|
intrEvent = new IntrEvent(this, true);
|
|
|
|
|
intrEvent->schedule(intrTick);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
Base::cpuInterrupt()
|
|
|
|
|
{
|
|
|
|
|
assert(intrTick == curTick);
|
|
|
|
|
|
|
|
|
|
// Whether or not there's a pending interrupt, we don't care about
|
|
|
|
|
// it anymore
|
|
|
|
|
intrEvent = 0;
|
|
|
|
|
intrTick = 0;
|
|
|
|
|
|
|
|
|
|
// Don't send an interrupt if there's already one
|
|
|
|
|
if (cpuPendingIntr) {
|
|
|
|
|
DPRINTF(EthernetIntr,
|
|
|
|
|
"would send an interrupt now, but there's already pending\n");
|
|
|
|
|
} else {
|
|
|
|
|
// Send interrupt
|
|
|
|
|
cpuPendingIntr = true;
|
|
|
|
|
|
|
|
|
|
DPRINTF(EthernetIntr, "posting interrupt\n");
|
|
|
|
|
intrPost();
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
Base::cpuIntrClear()
|
|
|
|
|
{
|
|
|
|
|
if (!cpuPendingIntr)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
if (intrEvent) {
|
|
|
|
|
intrEvent->squash();
|
|
|
|
|
intrEvent = 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
intrTick = 0;
|
|
|
|
|
|
|
|
|
|
cpuPendingIntr = false;
|
|
|
|
|
|
|
|
|
|
DPRINTF(EthernetIntr, "clearing cchip interrupt\n");
|
|
|
|
|
intrClear();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool
|
|
|
|
|
Base::cpuIntrPending() const
|
|
|
|
|
{ return cpuPendingIntr; }
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
Device::changeConfig(uint32_t newconf)
|
|
|
|
|
{
|
|
|
|
|
uint32_t changed = regs.Config ^ newconf;
|
|
|
|
|
if (!changed)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
regs.Config = newconf;
|
|
|
|
|
|
|
|
|
|
if ((changed & Regs::Config_IntEn)) {
|
|
|
|
|
cpuIntrEnable = regs.Config & Regs::Config_IntEn;
|
|
|
|
|
if (cpuIntrEnable) {
|
|
|
|
|
if (regs.IntrStatus & regs.IntrMask)
|
|
|
|
|
cpuIntrPost(curTick);
|
|
|
|
|
} else {
|
|
|
|
|
cpuIntrClear();
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if ((changed & Regs::Config_TxEn)) {
|
|
|
|
|
txEnable = regs.Config & Regs::Config_TxEn;
|
|
|
|
|
if (txEnable)
|
|
|
|
|
txKick();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if ((changed & Regs::Config_RxEn)) {
|
|
|
|
|
rxEnable = regs.Config & Regs::Config_RxEn;
|
|
|
|
|
if (rxEnable)
|
|
|
|
|
rxKick();
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
void
|
|
|
|
|
Device::command(uint32_t command)
|
|
|
|
|
{
|
2005-11-25 19:33:36 +01:00
|
|
|
if (command & Regs::Command_Intr)
|
|
|
|
|
devIntrPost(Regs::Intr_Soft);
|
|
|
|
|
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
if (command & Regs::Command_Reset)
|
|
|
|
|
reset();
|
|
|
|
|
}
|
|
|
|
|
|
2004-11-13 23:10:48 +01:00
|
|
|
void
|
|
|
|
|
Device::reset()
|
|
|
|
|
{
|
|
|
|
|
using namespace Regs;
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
|
2004-11-13 23:10:48 +01:00
|
|
|
memset(®s, 0, sizeof(regs));
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
|
|
|
|
|
regs.Config = 0;
|
2005-11-25 19:33:36 +01:00
|
|
|
if (params()->rx_thread)
|
|
|
|
|
regs.Config |= Config_RxThread;
|
|
|
|
|
if (params()->tx_thread)
|
|
|
|
|
regs.Config |= Config_TxThread;
|
2006-03-03 20:17:48 +01:00
|
|
|
if (params()->rss)
|
|
|
|
|
regs.Config |= Config_RSS;
|
2006-04-26 23:52:33 +02:00
|
|
|
if (params()->zero_copy)
|
|
|
|
|
regs.Config |= Config_ZeroCopy;
|
|
|
|
|
if (params()->delay_copy)
|
|
|
|
|
regs.Config |= Config_DelayCopy;
|
|
|
|
|
if (params()->virtual_addr)
|
|
|
|
|
regs.Config |= Config_Vaddr;
|
|
|
|
|
|
|
|
|
|
if (params()->delay_copy && params()->zero_copy)
|
|
|
|
|
panic("Can't delay copy and zero copy");
|
|
|
|
|
|
2005-11-25 19:33:36 +01:00
|
|
|
regs.IntrMask = Intr_Soft | Intr_RxHigh | Intr_RxPacket | Intr_TxLow;
|
2004-11-13 23:10:48 +01:00
|
|
|
regs.RxMaxCopy = params()->rx_max_copy;
|
|
|
|
|
regs.TxMaxCopy = params()->tx_max_copy;
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
regs.RxMaxIntr = params()->rx_max_intr;
|
2006-04-26 23:52:33 +02:00
|
|
|
regs.VirtualCount = params()->virtual_count;
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
regs.RxFifoSize = params()->rx_fifo_size;
|
|
|
|
|
regs.TxFifoSize = params()->tx_fifo_size;
|
|
|
|
|
regs.RxFifoMark = params()->rx_fifo_threshold;
|
|
|
|
|
regs.TxFifoMark = params()->tx_fifo_threshold;
|
|
|
|
|
regs.HwAddr = params()->eaddr;
|
2004-11-13 23:10:48 +01:00
|
|
|
|
2005-11-25 19:33:36 +01:00
|
|
|
rxList.clear();
|
2006-04-26 23:52:33 +02:00
|
|
|
rxBusy.clear();
|
|
|
|
|
rxActive = -1;
|
2005-11-25 19:33:36 +01:00
|
|
|
txList.clear();
|
|
|
|
|
|
2004-11-13 23:10:48 +01:00
|
|
|
rxState = rxIdle;
|
|
|
|
|
txState = txIdle;
|
|
|
|
|
|
|
|
|
|
rxFifo.clear();
|
2005-11-25 19:33:36 +01:00
|
|
|
rxFifoPtr = rxFifo.end();
|
2004-11-13 23:10:48 +01:00
|
|
|
txFifo.clear();
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
rxEmpty = false;
|
2006-04-26 23:52:33 +02:00
|
|
|
rxLow = true;
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
txFull = false;
|
2005-11-25 19:33:36 +01:00
|
|
|
|
|
|
|
|
int size = virtualRegs.size();
|
|
|
|
|
virtualRegs.clear();
|
|
|
|
|
virtualRegs.resize(size);
|
|
|
|
|
for (int i = 0; i < size; ++i)
|
|
|
|
|
virtualRegs[i].rxPacket = rxFifo.end();
|
2004-11-13 23:10:48 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
2006-04-25 01:31:50 +02:00
|
|
|
Device::rxDmaDone()
|
2004-11-13 23:10:48 +01:00
|
|
|
{
|
|
|
|
|
assert(rxState == rxCopy);
|
|
|
|
|
rxState = rxCopyDone;
|
2006-04-25 16:57:08 +02:00
|
|
|
DPRINTF(EthernetDMA, "end rx dma write paddr=%#x len=%d\n",
|
2004-11-13 23:10:48 +01:00
|
|
|
rxDmaAddr, rxDmaLen);
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
DDUMP(EthernetData, rxDmaData, rxDmaLen);
|
|
|
|
|
|
|
|
|
|
// If the transmit state machine has a pending DMA, let it go first
|
|
|
|
|
if (txState == txBeginCopy)
|
|
|
|
|
txKick();
|
|
|
|
|
|
2004-11-13 23:10:48 +01:00
|
|
|
rxKick();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
Device::rxKick()
|
|
|
|
|
{
|
2006-04-26 23:52:33 +02:00
|
|
|
VirtualReg *vnic = NULL;
|
2005-11-25 19:33:36 +01:00
|
|
|
|
2006-04-25 16:40:35 +02:00
|
|
|
DPRINTF(EthernetSM, "rxKick: rxState=%s (rxFifo.size=%d)\n",
|
2004-11-13 23:10:48 +01:00
|
|
|
RxStateStrings[rxState], rxFifo.size());
|
|
|
|
|
|
|
|
|
|
if (rxKickTick > curTick) {
|
2006-04-25 16:40:35 +02:00
|
|
|
DPRINTF(EthernetSM, "rxKick: exiting, can't run till %d\n",
|
2004-11-13 23:10:48 +01:00
|
|
|
rxKickTick);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
next:
|
2005-11-25 19:33:36 +01:00
|
|
|
if (rxState == rxIdle)
|
2004-11-13 23:10:48 +01:00
|
|
|
goto exit;
|
|
|
|
|
|
2006-04-26 23:52:33 +02:00
|
|
|
if (rxActive == -1) {
|
|
|
|
|
if (rxState != rxFifoBlock)
|
|
|
|
|
panic("no active vnic while in state %s", RxStateStrings[rxState]);
|
2005-11-25 19:33:36 +01:00
|
|
|
|
2006-04-26 23:52:33 +02:00
|
|
|
DPRINTF(EthernetSM, "processing rxState=%s\n",
|
|
|
|
|
RxStateStrings[rxState]);
|
|
|
|
|
} else {
|
|
|
|
|
vnic = &virtualRegs[rxActive];
|
|
|
|
|
DPRINTF(EthernetSM,
|
|
|
|
|
"processing rxState=%s for vnic %d (rxunique %d)\n",
|
|
|
|
|
RxStateStrings[rxState], rxActive, vnic->rxUnique);
|
|
|
|
|
}
|
2005-11-25 19:33:36 +01:00
|
|
|
|
|
|
|
|
switch (rxState) {
|
2004-11-13 23:10:48 +01:00
|
|
|
case rxFifoBlock:
|
2006-04-26 23:52:33 +02:00
|
|
|
if (DTRACE(EthernetSM)) {
|
|
|
|
|
PacketFifo::iterator end = rxFifo.end();
|
|
|
|
|
int size = virtualRegs.size();
|
|
|
|
|
for (int i = 0; i < size; ++i) {
|
|
|
|
|
VirtualReg *vn = &virtualRegs[i];
|
|
|
|
|
if (vn->rxPacket != end &&
|
|
|
|
|
!Regs::get_RxDone_Busy(vn->RxDone)) {
|
|
|
|
|
DPRINTF(EthernetSM,
|
|
|
|
|
"vnic %d (rxunique %d), has outstanding packet %d\n",
|
|
|
|
|
i, vn->rxUnique,
|
|
|
|
|
rxFifo.countPacketsBefore(vn->rxPacket));
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (!rxBusy.empty()) {
|
|
|
|
|
rxActive = rxBusy.front();
|
|
|
|
|
rxBusy.pop_front();
|
|
|
|
|
vnic = &virtualRegs[rxActive];
|
|
|
|
|
|
|
|
|
|
if (vnic->rxPacket == rxFifo.end())
|
|
|
|
|
panic("continuing vnic without packet\n");
|
|
|
|
|
|
|
|
|
|
DPRINTF(EthernetSM,
|
|
|
|
|
"continue processing for vnic %d (rxunique %d)\n",
|
|
|
|
|
rxActive, vnic->rxUnique);
|
|
|
|
|
|
2004-11-13 23:10:48 +01:00
|
|
|
rxState = rxBeginCopy;
|
2006-04-26 23:52:33 +02:00
|
|
|
|
2004-11-13 23:10:48 +01:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
2005-11-25 19:33:36 +01:00
|
|
|
if (rxFifoPtr == rxFifo.end()) {
|
2004-11-13 23:10:48 +01:00
|
|
|
DPRINTF(EthernetSM, "receive waiting for data. Nothing to do.\n");
|
|
|
|
|
goto exit;
|
|
|
|
|
}
|
|
|
|
|
|
2006-04-26 23:52:33 +02:00
|
|
|
if (rxList.empty())
|
|
|
|
|
panic("Not idle, but nothing to do!");
|
|
|
|
|
|
2005-11-25 19:33:36 +01:00
|
|
|
assert(!rxFifo.empty());
|
|
|
|
|
|
2006-04-26 23:52:33 +02:00
|
|
|
rxActive = rxList.front();
|
|
|
|
|
rxList.pop_front();
|
|
|
|
|
vnic = &virtualRegs[rxActive];
|
|
|
|
|
|
|
|
|
|
DPRINTF(EthernetSM,
|
|
|
|
|
"processing new packet for vnic %d (rxunique %d)\n",
|
|
|
|
|
rxActive, vnic->rxUnique);
|
|
|
|
|
|
2004-11-13 23:10:48 +01:00
|
|
|
// Grab a new packet from the fifo.
|
2005-11-25 19:33:36 +01:00
|
|
|
vnic->rxPacket = rxFifoPtr++;
|
|
|
|
|
vnic->rxPacketOffset = 0;
|
|
|
|
|
vnic->rxPacketBytes = (*vnic->rxPacket)->length;
|
|
|
|
|
assert(vnic->rxPacketBytes);
|
2004-11-13 23:10:48 +01:00
|
|
|
|
2005-11-25 19:33:36 +01:00
|
|
|
vnic->rxDoneData = 0;
|
2004-11-13 23:10:48 +01:00
|
|
|
/* scope for variables */ {
|
2005-11-25 19:33:36 +01:00
|
|
|
IpPtr ip(*vnic->rxPacket);
|
2004-11-13 23:10:48 +01:00
|
|
|
if (ip) {
|
2006-04-25 16:57:08 +02:00
|
|
|
DPRINTF(Ethernet, "ID is %d\n", ip->id());
|
2005-11-25 19:33:36 +01:00
|
|
|
vnic->rxDoneData |= Regs::RxDone_IpPacket;
|
2004-11-13 23:10:48 +01:00
|
|
|
rxIpChecksums++;
|
|
|
|
|
if (cksum(ip) != 0) {
|
|
|
|
|
DPRINTF(EthernetCksum, "Rx IP Checksum Error\n");
|
2005-11-25 19:33:36 +01:00
|
|
|
vnic->rxDoneData |= Regs::RxDone_IpError;
|
2004-11-13 23:10:48 +01:00
|
|
|
}
|
|
|
|
|
TcpPtr tcp(ip);
|
|
|
|
|
UdpPtr udp(ip);
|
|
|
|
|
if (tcp) {
|
2006-04-25 16:40:35 +02:00
|
|
|
DPRINTF(Ethernet,
|
|
|
|
|
"Src Port=%d, Dest Port=%d, Seq=%d, Ack=%d\n",
|
|
|
|
|
tcp->sport(), tcp->dport(), tcp->seq(),
|
|
|
|
|
tcp->ack());
|
2005-11-25 19:33:36 +01:00
|
|
|
vnic->rxDoneData |= Regs::RxDone_TcpPacket;
|
2004-11-13 23:10:48 +01:00
|
|
|
rxTcpChecksums++;
|
|
|
|
|
if (cksum(tcp) != 0) {
|
|
|
|
|
DPRINTF(EthernetCksum, "Rx TCP Checksum Error\n");
|
2005-11-25 19:33:36 +01:00
|
|
|
vnic->rxDoneData |= Regs::RxDone_TcpError;
|
2004-11-13 23:10:48 +01:00
|
|
|
}
|
|
|
|
|
} else if (udp) {
|
2005-11-25 19:33:36 +01:00
|
|
|
vnic->rxDoneData |= Regs::RxDone_UdpPacket;
|
2004-11-13 23:10:48 +01:00
|
|
|
rxUdpChecksums++;
|
|
|
|
|
if (cksum(udp) != 0) {
|
|
|
|
|
DPRINTF(EthernetCksum, "Rx UDP Checksum Error\n");
|
2005-11-25 19:33:36 +01:00
|
|
|
vnic->rxDoneData |= Regs::RxDone_UdpError;
|
2004-11-13 23:10:48 +01:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
rxState = rxBeginCopy;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case rxBeginCopy:
|
2006-07-13 02:22:07 +02:00
|
|
|
if (dmaPending() || getState() != Running)
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
goto exit;
|
|
|
|
|
|
2006-04-25 01:31:50 +02:00
|
|
|
rxDmaAddr = params()->platform->pciToDma(
|
|
|
|
|
Regs::get_RxData_Addr(vnic->RxData));
|
|
|
|
|
rxDmaLen = std::min<int>(Regs::get_RxData_Len(vnic->RxData),
|
2005-11-25 19:33:36 +01:00
|
|
|
vnic->rxPacketBytes);
|
|
|
|
|
rxDmaData = (*vnic->rxPacket)->data + vnic->rxPacketOffset;
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
rxState = rxCopy;
|
2006-04-26 23:52:33 +02:00
|
|
|
if (rxDmaAddr == 1LL) {
|
|
|
|
|
rxState = rxCopyDone;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
2004-11-13 23:10:48 +01:00
|
|
|
|
2006-04-25 01:31:50 +02:00
|
|
|
dmaWrite(rxDmaAddr, rxDmaLen, &rxDmaEvent, rxDmaData);
|
2004-11-13 23:10:48 +01:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case rxCopy:
|
|
|
|
|
DPRINTF(EthernetSM, "receive machine still copying\n");
|
|
|
|
|
goto exit;
|
|
|
|
|
|
|
|
|
|
case rxCopyDone:
|
2006-04-26 23:52:33 +02:00
|
|
|
vnic->RxDone = vnic->rxDoneData;
|
2005-11-25 19:33:36 +01:00
|
|
|
vnic->RxDone |= Regs::RxDone_Complete;
|
2004-11-13 23:10:48 +01:00
|
|
|
|
2005-11-25 19:33:36 +01:00
|
|
|
if (vnic->rxPacketBytes == rxDmaLen) {
|
2006-04-26 23:52:33 +02:00
|
|
|
// Packet is complete. Indicate how many bytes were copied
|
|
|
|
|
vnic->RxDone = Regs::set_RxDone_CopyLen(vnic->RxDone, rxDmaLen);
|
|
|
|
|
|
|
|
|
|
DPRINTF(EthernetSM,
|
|
|
|
|
"rxKick: packet complete on vnic %d (rxunique %d)\n",
|
|
|
|
|
rxActive, vnic->rxUnique);
|
2005-11-25 19:33:36 +01:00
|
|
|
rxFifo.remove(vnic->rxPacket);
|
|
|
|
|
vnic->rxPacket = rxFifo.end();
|
2004-11-13 23:10:48 +01:00
|
|
|
} else {
|
2005-11-25 19:33:36 +01:00
|
|
|
vnic->rxPacketBytes -= rxDmaLen;
|
|
|
|
|
vnic->rxPacketOffset += rxDmaLen;
|
2006-04-26 23:52:33 +02:00
|
|
|
vnic->RxDone |= Regs::RxDone_More;
|
|
|
|
|
vnic->RxDone = Regs::set_RxDone_CopyLen(vnic->RxDone,
|
|
|
|
|
vnic->rxPacketBytes);
|
2005-11-29 00:40:58 +01:00
|
|
|
DPRINTF(EthernetSM,
|
2006-04-26 23:52:33 +02:00
|
|
|
"rxKick: packet not complete on vnic %d (rxunique %d): "
|
|
|
|
|
"%d bytes left\n",
|
|
|
|
|
rxActive, vnic->rxUnique, vnic->rxPacketBytes);
|
2005-11-25 19:33:36 +01:00
|
|
|
}
|
|
|
|
|
|
2006-04-26 23:52:33 +02:00
|
|
|
rxActive = -1;
|
|
|
|
|
rxState = rxBusy.empty() && rxList.empty() ? rxIdle : rxFifoBlock;
|
2005-11-25 19:33:36 +01:00
|
|
|
|
|
|
|
|
if (rxFifo.empty()) {
|
|
|
|
|
devIntrPost(Regs::Intr_RxEmpty);
|
|
|
|
|
rxEmpty = true;
|
2004-11-13 23:10:48 +01:00
|
|
|
}
|
|
|
|
|
|
2006-04-26 23:52:33 +02:00
|
|
|
if (rxFifo.size() < params()->rx_fifo_low_mark)
|
|
|
|
|
rxLow = true;
|
|
|
|
|
|
|
|
|
|
if (rxFifo.size() > params()->rx_fifo_threshold)
|
|
|
|
|
rxLow = false;
|
|
|
|
|
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
devIntrPost(Regs::Intr_RxDMA);
|
2004-11-13 23:10:48 +01:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
panic("Invalid rxState!");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
DPRINTF(EthernetSM, "entering next rxState=%s\n",
|
|
|
|
|
RxStateStrings[rxState]);
|
|
|
|
|
|
|
|
|
|
goto next;
|
|
|
|
|
|
|
|
|
|
exit:
|
|
|
|
|
/**
|
|
|
|
|
* @todo do we want to schedule a future kick?
|
|
|
|
|
*/
|
|
|
|
|
DPRINTF(EthernetSM, "rx state machine exited rxState=%s\n",
|
|
|
|
|
RxStateStrings[rxState]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
2006-04-25 01:31:50 +02:00
|
|
|
Device::txDmaDone()
|
2004-11-13 23:10:48 +01:00
|
|
|
{
|
|
|
|
|
assert(txState == txCopy);
|
|
|
|
|
txState = txCopyDone;
|
|
|
|
|
DPRINTF(EthernetDMA, "tx dma read paddr=%#x len=%d\n",
|
|
|
|
|
txDmaAddr, txDmaLen);
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
DDUMP(EthernetData, txDmaData, txDmaLen);
|
|
|
|
|
|
|
|
|
|
// If the receive state machine has a pending DMA, let it go first
|
|
|
|
|
if (rxState == rxBeginCopy)
|
|
|
|
|
rxKick();
|
|
|
|
|
|
2004-11-13 23:10:48 +01:00
|
|
|
txKick();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
Device::transmit()
|
|
|
|
|
{
|
|
|
|
|
if (txFifo.empty()) {
|
|
|
|
|
DPRINTF(Ethernet, "nothing to transmit\n");
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
uint32_t interrupts;
|
2006-04-25 01:31:50 +02:00
|
|
|
EthPacketPtr packet = txFifo.front();
|
2004-11-13 23:10:48 +01:00
|
|
|
if (!interface->sendPacket(packet)) {
|
|
|
|
|
DPRINTF(Ethernet, "Packet Transmit: failed txFifo available %d\n",
|
|
|
|
|
txFifo.avail());
|
|
|
|
|
goto reschedule;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
txFifo.pop();
|
|
|
|
|
#if TRACING_ON
|
|
|
|
|
if (DTRACE(Ethernet)) {
|
|
|
|
|
IpPtr ip(packet);
|
|
|
|
|
if (ip) {
|
|
|
|
|
DPRINTF(Ethernet, "ID is %d\n", ip->id());
|
|
|
|
|
TcpPtr tcp(ip);
|
|
|
|
|
if (tcp) {
|
2006-04-25 16:57:08 +02:00
|
|
|
DPRINTF(Ethernet,
|
|
|
|
|
"Src Port=%d, Dest Port=%d, Seq=%d, Ack=%d\n",
|
|
|
|
|
tcp->sport(), tcp->dport(), tcp->seq(),
|
|
|
|
|
tcp->ack());
|
2004-11-13 23:10:48 +01:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
DDUMP(EthernetData, packet->data, packet->length);
|
2004-11-13 23:10:48 +01:00
|
|
|
txBytes += packet->length;
|
|
|
|
|
txPackets++;
|
|
|
|
|
|
|
|
|
|
DPRINTF(Ethernet, "Packet Transmit: successful txFifo Available %d\n",
|
|
|
|
|
txFifo.avail());
|
|
|
|
|
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
interrupts = Regs::Intr_TxPacket;
|
|
|
|
|
if (txFifo.size() < regs.TxFifoMark)
|
|
|
|
|
interrupts |= Regs::Intr_TxLow;
|
|
|
|
|
devIntrPost(interrupts);
|
2004-11-13 23:10:48 +01:00
|
|
|
|
|
|
|
|
reschedule:
|
|
|
|
|
if (!txFifo.empty() && !txEvent.scheduled()) {
|
|
|
|
|
DPRINTF(Ethernet, "reschedule transmit\n");
|
Make the notion of a global event tick independent of the actual
CPU cycle ticks. This allows the user to have CPUs of different
frequencies, and also allows frequencies and latencies that are
not evenly divisible by the CPU frequency. For now, the CPU
frequency is still set to the global frequency, but soon, we'll
hopefully make the global frequency fixed at something like 1THz
and set all other frequencies independently.
arch/alpha/ev5.cc:
The cycles counter is based on the current cpu cycle.
cpu/base_cpu.cc:
frequency isn't the cpu parameter anymore, cycleTime is.
cpu/base_cpu.hh:
frequency isn't the cpu parameter anymore, cycleTime is.
create several public functions for getting the cpu frequency
and the numbers of ticks for a given number of cycles, etc.
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/trace/trace_cpu.cc:
Now that ticks aren't cpu cycles, fixup code to advance
by the proper number of ticks.
cpu/memtest/memtest.hh:
cpu/trace/trace_cpu.hh:
Provide a function to get the number of ticks for a given
number of cycles.
dev/alpha_console.cc:
Update for changes in the way that frequencies and latencies are
accessed. Move some stuff to init()
dev/alpha_console.hh:
Need a pointer to the system and the cpu to get the frequency
so we can pass the info to the console code.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
dev/ide_disk.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
Add some extra debugging printfs
dev/platform.cc:
dev/sinic.cc:
dev/sinic.hh:
outline the constructor and destructor
dev/platform.hh:
outline the constructor and destructor.
don't keep track of the interrupt frequency. Only provide the
accessor function.
dev/tsunami.cc:
dev/tsunami.hh:
outline the constructor and destructor
Don't set the interrupt frequency here. Get it from the actual device
that does the interrupting.
dev/tsunami_io.cc:
dev/tsunami_io.hh:
Make the interrupt interval a configuration parameter. (And convert
the interval to the new latency/frequency stuff in the python)
kern/linux/linux_system.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
kern/tru64/tru64_system.cc:
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
python/m5/config.py:
Fix support for cycle_time relative latencies and frequencies.
Add support for getting a NetworkBandwidth or a MemoryBandwidth.
python/m5/objects/BaseCPU.mpy:
All CPUs now have a cycle_time. The default is the global frequency,
but it is now possible to set the global frequency to some large value
(like 1THz) and set each CPU frequency independently.
python/m5/objects/BaseCache.mpy:
python/m5/objects/Ide.mpy:
Make this a Latency parameter
python/m5/objects/BaseSystem.mpy:
We need to pass the boot CPU's frequency to the system
python/m5/objects/Ethernet.mpy:
Update parameter types to use latency and bandwidth types
python/m5/objects/Platform.mpy:
this frequency isn't needed. We get it from the clock interrupt.
python/m5/objects/Tsunami.mpy:
The clock generator should hold the frequency
sim/eventq.hh:
Need to remove this assertion because the writeback event
queue is different from the CPU's event queue which can cause
this assertion to fail.
sim/process.cc:
Fix comment.
sim/system.hh:
Struct member to hold the boot CPU's frequency.
sim/universe.cc:
remove unneeded variable.
--HG--
extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
2005-04-11 21:32:06 +02:00
|
|
|
txEvent.schedule(curTick + retryTime);
|
2004-11-13 23:10:48 +01:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
Device::txKick()
|
|
|
|
|
{
|
2005-11-25 19:33:36 +01:00
|
|
|
VirtualReg *vnic;
|
2006-04-25 16:40:35 +02:00
|
|
|
DPRINTF(EthernetSM, "txKick: txState=%s (txFifo.size=%d)\n",
|
2004-11-13 23:10:48 +01:00
|
|
|
TxStateStrings[txState], txFifo.size());
|
|
|
|
|
|
|
|
|
|
if (txKickTick > curTick) {
|
2006-04-25 16:40:35 +02:00
|
|
|
DPRINTF(EthernetSM, "txKick: exiting, can't run till %d\n",
|
2004-11-13 23:10:48 +01:00
|
|
|
txKickTick);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
next:
|
2005-11-25 19:33:36 +01:00
|
|
|
if (txState == txIdle)
|
2004-11-13 23:10:48 +01:00
|
|
|
goto exit;
|
|
|
|
|
|
2005-11-25 19:33:36 +01:00
|
|
|
assert(!txList.empty());
|
|
|
|
|
vnic = &virtualRegs[txList.front()];
|
|
|
|
|
|
|
|
|
|
switch (txState) {
|
2004-11-13 23:10:48 +01:00
|
|
|
case txFifoBlock:
|
2006-04-25 16:57:08 +02:00
|
|
|
assert(Regs::get_TxDone_Busy(vnic->TxDone));
|
2004-11-13 23:10:48 +01:00
|
|
|
if (!txPacket) {
|
|
|
|
|
// Grab a new packet from the fifo.
|
2006-04-25 01:31:50 +02:00
|
|
|
txPacket = new EthPacketData(16384);
|
2005-11-25 19:33:36 +01:00
|
|
|
txPacketOffset = 0;
|
2004-11-13 23:10:48 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (txFifo.avail() - txPacket->length <
|
2005-11-25 19:33:36 +01:00
|
|
|
Regs::get_TxData_Len(vnic->TxData)) {
|
2004-11-13 23:10:48 +01:00
|
|
|
DPRINTF(EthernetSM, "transmit fifo full. Nothing to do.\n");
|
|
|
|
|
goto exit;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
txState = txBeginCopy;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case txBeginCopy:
|
2006-07-13 02:22:07 +02:00
|
|
|
if (dmaPending() || getState() != Running)
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
goto exit;
|
|
|
|
|
|
2006-04-25 01:31:50 +02:00
|
|
|
txDmaAddr = params()->platform->pciToDma(
|
|
|
|
|
Regs::get_TxData_Addr(vnic->TxData));
|
2005-11-25 19:33:36 +01:00
|
|
|
txDmaLen = Regs::get_TxData_Len(vnic->TxData);
|
|
|
|
|
txDmaData = txPacket->data + txPacketOffset;
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
txState = txCopy;
|
2004-11-13 23:10:48 +01:00
|
|
|
|
2006-04-25 01:31:50 +02:00
|
|
|
dmaRead(txDmaAddr, txDmaLen, &txDmaEvent, txDmaData);
|
2004-11-13 23:10:48 +01:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case txCopy:
|
|
|
|
|
DPRINTF(EthernetSM, "transmit machine still copying\n");
|
|
|
|
|
goto exit;
|
|
|
|
|
|
|
|
|
|
case txCopyDone:
|
2005-11-25 19:33:36 +01:00
|
|
|
vnic->TxDone = txDmaLen | Regs::TxDone_Complete;
|
2004-11-13 23:10:48 +01:00
|
|
|
txPacket->length += txDmaLen;
|
2005-11-25 19:33:36 +01:00
|
|
|
if ((vnic->TxData & Regs::TxData_More)) {
|
|
|
|
|
txPacketOffset += txDmaLen;
|
|
|
|
|
txState = txIdle;
|
|
|
|
|
devIntrPost(Regs::Intr_TxDMA);
|
|
|
|
|
break;
|
|
|
|
|
}
|
2004-11-13 23:10:48 +01:00
|
|
|
|
2005-11-25 19:33:36 +01:00
|
|
|
assert(txPacket->length <= txFifo.avail());
|
|
|
|
|
if ((vnic->TxData & Regs::TxData_Checksum)) {
|
|
|
|
|
IpPtr ip(txPacket);
|
|
|
|
|
if (ip) {
|
|
|
|
|
TcpPtr tcp(ip);
|
|
|
|
|
if (tcp) {
|
|
|
|
|
tcp->sum(0);
|
|
|
|
|
tcp->sum(cksum(tcp));
|
|
|
|
|
txTcpChecksums++;
|
|
|
|
|
}
|
2004-11-13 23:10:48 +01:00
|
|
|
|
2005-11-25 19:33:36 +01:00
|
|
|
UdpPtr udp(ip);
|
|
|
|
|
if (udp) {
|
|
|
|
|
udp->sum(0);
|
|
|
|
|
udp->sum(cksum(udp));
|
|
|
|
|
txUdpChecksums++;
|
2004-11-13 23:10:48 +01:00
|
|
|
}
|
2005-11-25 19:33:36 +01:00
|
|
|
|
|
|
|
|
ip->sum(0);
|
|
|
|
|
ip->sum(cksum(ip));
|
|
|
|
|
txIpChecksums++;
|
2004-11-13 23:10:48 +01:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2005-11-25 19:33:36 +01:00
|
|
|
txFifo.push(txPacket);
|
|
|
|
|
if (txFifo.avail() < regs.TxMaxCopy) {
|
|
|
|
|
devIntrPost(Regs::Intr_TxFull);
|
|
|
|
|
txFull = true;
|
|
|
|
|
}
|
|
|
|
|
txPacket = 0;
|
|
|
|
|
transmit();
|
|
|
|
|
txList.pop_front();
|
|
|
|
|
txState = txList.empty() ? txIdle : txFifoBlock;
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
devIntrPost(Regs::Intr_TxDMA);
|
2004-11-13 23:10:48 +01:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
panic("Invalid txState!");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
DPRINTF(EthernetSM, "entering next txState=%s\n",
|
|
|
|
|
TxStateStrings[txState]);
|
|
|
|
|
|
|
|
|
|
goto next;
|
|
|
|
|
|
|
|
|
|
exit:
|
|
|
|
|
/**
|
|
|
|
|
* @todo do we want to schedule a future kick?
|
|
|
|
|
*/
|
|
|
|
|
DPRINTF(EthernetSM, "tx state machine exited txState=%s\n",
|
|
|
|
|
TxStateStrings[txState]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
Device::transferDone()
|
|
|
|
|
{
|
|
|
|
|
if (txFifo.empty()) {
|
|
|
|
|
DPRINTF(Ethernet, "transfer complete: txFifo empty...nothing to do\n");
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
DPRINTF(Ethernet, "transfer complete: data in txFifo...schedule xmit\n");
|
|
|
|
|
|
|
|
|
|
if (txEvent.scheduled())
|
Make the notion of a global event tick independent of the actual
CPU cycle ticks. This allows the user to have CPUs of different
frequencies, and also allows frequencies and latencies that are
not evenly divisible by the CPU frequency. For now, the CPU
frequency is still set to the global frequency, but soon, we'll
hopefully make the global frequency fixed at something like 1THz
and set all other frequencies independently.
arch/alpha/ev5.cc:
The cycles counter is based on the current cpu cycle.
cpu/base_cpu.cc:
frequency isn't the cpu parameter anymore, cycleTime is.
cpu/base_cpu.hh:
frequency isn't the cpu parameter anymore, cycleTime is.
create several public functions for getting the cpu frequency
and the numbers of ticks for a given number of cycles, etc.
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/trace/trace_cpu.cc:
Now that ticks aren't cpu cycles, fixup code to advance
by the proper number of ticks.
cpu/memtest/memtest.hh:
cpu/trace/trace_cpu.hh:
Provide a function to get the number of ticks for a given
number of cycles.
dev/alpha_console.cc:
Update for changes in the way that frequencies and latencies are
accessed. Move some stuff to init()
dev/alpha_console.hh:
Need a pointer to the system and the cpu to get the frequency
so we can pass the info to the console code.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
dev/ide_disk.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
Add some extra debugging printfs
dev/platform.cc:
dev/sinic.cc:
dev/sinic.hh:
outline the constructor and destructor
dev/platform.hh:
outline the constructor and destructor.
don't keep track of the interrupt frequency. Only provide the
accessor function.
dev/tsunami.cc:
dev/tsunami.hh:
outline the constructor and destructor
Don't set the interrupt frequency here. Get it from the actual device
that does the interrupting.
dev/tsunami_io.cc:
dev/tsunami_io.hh:
Make the interrupt interval a configuration parameter. (And convert
the interval to the new latency/frequency stuff in the python)
kern/linux/linux_system.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
kern/tru64/tru64_system.cc:
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
python/m5/config.py:
Fix support for cycle_time relative latencies and frequencies.
Add support for getting a NetworkBandwidth or a MemoryBandwidth.
python/m5/objects/BaseCPU.mpy:
All CPUs now have a cycle_time. The default is the global frequency,
but it is now possible to set the global frequency to some large value
(like 1THz) and set each CPU frequency independently.
python/m5/objects/BaseCache.mpy:
python/m5/objects/Ide.mpy:
Make this a Latency parameter
python/m5/objects/BaseSystem.mpy:
We need to pass the boot CPU's frequency to the system
python/m5/objects/Ethernet.mpy:
Update parameter types to use latency and bandwidth types
python/m5/objects/Platform.mpy:
this frequency isn't needed. We get it from the clock interrupt.
python/m5/objects/Tsunami.mpy:
The clock generator should hold the frequency
sim/eventq.hh:
Need to remove this assertion because the writeback event
queue is different from the CPU's event queue which can cause
this assertion to fail.
sim/process.cc:
Fix comment.
sim/system.hh:
Struct member to hold the boot CPU's frequency.
sim/universe.cc:
remove unneeded variable.
--HG--
extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
2005-04-11 21:32:06 +02:00
|
|
|
txEvent.reschedule(curTick + cycles(1));
|
2004-11-13 23:10:48 +01:00
|
|
|
else
|
Make the notion of a global event tick independent of the actual
CPU cycle ticks. This allows the user to have CPUs of different
frequencies, and also allows frequencies and latencies that are
not evenly divisible by the CPU frequency. For now, the CPU
frequency is still set to the global frequency, but soon, we'll
hopefully make the global frequency fixed at something like 1THz
and set all other frequencies independently.
arch/alpha/ev5.cc:
The cycles counter is based on the current cpu cycle.
cpu/base_cpu.cc:
frequency isn't the cpu parameter anymore, cycleTime is.
cpu/base_cpu.hh:
frequency isn't the cpu parameter anymore, cycleTime is.
create several public functions for getting the cpu frequency
and the numbers of ticks for a given number of cycles, etc.
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/trace/trace_cpu.cc:
Now that ticks aren't cpu cycles, fixup code to advance
by the proper number of ticks.
cpu/memtest/memtest.hh:
cpu/trace/trace_cpu.hh:
Provide a function to get the number of ticks for a given
number of cycles.
dev/alpha_console.cc:
Update for changes in the way that frequencies and latencies are
accessed. Move some stuff to init()
dev/alpha_console.hh:
Need a pointer to the system and the cpu to get the frequency
so we can pass the info to the console code.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
dev/ide_disk.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
Add some extra debugging printfs
dev/platform.cc:
dev/sinic.cc:
dev/sinic.hh:
outline the constructor and destructor
dev/platform.hh:
outline the constructor and destructor.
don't keep track of the interrupt frequency. Only provide the
accessor function.
dev/tsunami.cc:
dev/tsunami.hh:
outline the constructor and destructor
Don't set the interrupt frequency here. Get it from the actual device
that does the interrupting.
dev/tsunami_io.cc:
dev/tsunami_io.hh:
Make the interrupt interval a configuration parameter. (And convert
the interval to the new latency/frequency stuff in the python)
kern/linux/linux_system.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
kern/tru64/tru64_system.cc:
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
python/m5/config.py:
Fix support for cycle_time relative latencies and frequencies.
Add support for getting a NetworkBandwidth or a MemoryBandwidth.
python/m5/objects/BaseCPU.mpy:
All CPUs now have a cycle_time. The default is the global frequency,
but it is now possible to set the global frequency to some large value
(like 1THz) and set each CPU frequency independently.
python/m5/objects/BaseCache.mpy:
python/m5/objects/Ide.mpy:
Make this a Latency parameter
python/m5/objects/BaseSystem.mpy:
We need to pass the boot CPU's frequency to the system
python/m5/objects/Ethernet.mpy:
Update parameter types to use latency and bandwidth types
python/m5/objects/Platform.mpy:
this frequency isn't needed. We get it from the clock interrupt.
python/m5/objects/Tsunami.mpy:
The clock generator should hold the frequency
sim/eventq.hh:
Need to remove this assertion because the writeback event
queue is different from the CPU's event queue which can cause
this assertion to fail.
sim/process.cc:
Fix comment.
sim/system.hh:
Struct member to hold the boot CPU's frequency.
sim/universe.cc:
remove unneeded variable.
--HG--
extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
2005-04-11 21:32:06 +02:00
|
|
|
txEvent.schedule(curTick + cycles(1));
|
2004-11-13 23:10:48 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool
|
2006-04-25 01:31:50 +02:00
|
|
|
Device::rxFilter(const EthPacketPtr &packet)
|
2004-11-13 23:10:48 +01:00
|
|
|
{
|
|
|
|
|
if (!Regs::get_Config_Filter(regs.Config))
|
|
|
|
|
return false;
|
|
|
|
|
|
|
|
|
|
panic("receive filter not implemented\n");
|
|
|
|
|
bool drop = true;
|
|
|
|
|
|
|
|
|
|
#if 0
|
|
|
|
|
string type;
|
|
|
|
|
|
|
|
|
|
EthHdr *eth = packet->eth();
|
|
|
|
|
if (eth->unicast()) {
|
|
|
|
|
// If we're accepting all unicast addresses
|
|
|
|
|
if (acceptUnicast)
|
|
|
|
|
drop = false;
|
|
|
|
|
|
|
|
|
|
// If we make a perfect match
|
|
|
|
|
if (acceptPerfect && params->eaddr == eth.dst())
|
|
|
|
|
drop = false;
|
|
|
|
|
|
|
|
|
|
if (acceptArp && eth->type() == ETH_TYPE_ARP)
|
|
|
|
|
drop = false;
|
|
|
|
|
|
|
|
|
|
} else if (eth->broadcast()) {
|
|
|
|
|
// if we're accepting broadcasts
|
|
|
|
|
if (acceptBroadcast)
|
|
|
|
|
drop = false;
|
|
|
|
|
|
|
|
|
|
} else if (eth->multicast()) {
|
|
|
|
|
// if we're accepting all multicasts
|
|
|
|
|
if (acceptMulticast)
|
|
|
|
|
drop = false;
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (drop) {
|
|
|
|
|
DPRINTF(Ethernet, "rxFilter drop\n");
|
|
|
|
|
DDUMP(EthernetData, packet->data, packet->length);
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
return drop;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool
|
2006-04-25 01:31:50 +02:00
|
|
|
Device::recvPacket(EthPacketPtr packet)
|
2004-11-13 23:10:48 +01:00
|
|
|
{
|
|
|
|
|
rxBytes += packet->length;
|
|
|
|
|
rxPackets++;
|
|
|
|
|
|
|
|
|
|
DPRINTF(Ethernet, "Receiving packet from wire, rxFifo Available is %d\n",
|
|
|
|
|
rxFifo.avail());
|
|
|
|
|
|
|
|
|
|
if (!rxEnable) {
|
|
|
|
|
DPRINTF(Ethernet, "receive disabled...packet dropped\n");
|
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (rxFilter(packet)) {
|
|
|
|
|
DPRINTF(Ethernet, "packet filtered...dropped\n");
|
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
if (rxFifo.size() >= regs.RxFifoMark)
|
|
|
|
|
devIntrPost(Regs::Intr_RxHigh);
|
2004-11-13 23:10:48 +01:00
|
|
|
|
|
|
|
|
if (!rxFifo.push(packet)) {
|
|
|
|
|
DPRINTF(Ethernet,
|
|
|
|
|
"packet will not fit in receive buffer...packet dropped\n");
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
2005-11-25 19:33:36 +01:00
|
|
|
// If we were at the last element, back up one ot go to the new
|
|
|
|
|
// last element of the list.
|
|
|
|
|
if (rxFifoPtr == rxFifo.end())
|
|
|
|
|
--rxFifoPtr;
|
|
|
|
|
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
devIntrPost(Regs::Intr_RxPacket);
|
2004-11-13 23:10:48 +01:00
|
|
|
rxKick();
|
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
|
2006-07-13 02:22:07 +02:00
|
|
|
void
|
|
|
|
|
Device::resume()
|
|
|
|
|
{
|
|
|
|
|
SimObject::resume();
|
|
|
|
|
|
|
|
|
|
// During drain we could have left the state machines in a waiting state and
|
|
|
|
|
// they wouldn't get out until some other event occured to kick them.
|
|
|
|
|
// This way they'll get out immediately
|
|
|
|
|
txKick();
|
|
|
|
|
rxKick();
|
|
|
|
|
}
|
|
|
|
|
|
2004-11-13 23:10:48 +01:00
|
|
|
//=====================================================================
|
|
|
|
|
//
|
|
|
|
|
//
|
|
|
|
|
void
|
2006-04-25 01:31:50 +02:00
|
|
|
Base::serialize(std::ostream &os)
|
2004-11-13 23:10:48 +01:00
|
|
|
{
|
|
|
|
|
// Serialize the PciDev base class
|
|
|
|
|
PciDev::serialize(os);
|
|
|
|
|
|
|
|
|
|
SERIALIZE_SCALAR(rxEnable);
|
|
|
|
|
SERIALIZE_SCALAR(txEnable);
|
|
|
|
|
SERIALIZE_SCALAR(cpuIntrEnable);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Keep track of pending interrupt status.
|
|
|
|
|
*/
|
|
|
|
|
SERIALIZE_SCALAR(intrTick);
|
|
|
|
|
SERIALIZE_SCALAR(cpuPendingIntr);
|
|
|
|
|
Tick intrEventTick = 0;
|
|
|
|
|
if (intrEvent)
|
|
|
|
|
intrEventTick = intrEvent->when();
|
|
|
|
|
SERIALIZE_SCALAR(intrEventTick);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
Base::unserialize(Checkpoint *cp, const std::string §ion)
|
|
|
|
|
{
|
|
|
|
|
// Unserialize the PciDev base class
|
|
|
|
|
PciDev::unserialize(cp, section);
|
|
|
|
|
|
|
|
|
|
UNSERIALIZE_SCALAR(rxEnable);
|
|
|
|
|
UNSERIALIZE_SCALAR(txEnable);
|
|
|
|
|
UNSERIALIZE_SCALAR(cpuIntrEnable);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Keep track of pending interrupt status.
|
|
|
|
|
*/
|
|
|
|
|
UNSERIALIZE_SCALAR(intrTick);
|
|
|
|
|
UNSERIALIZE_SCALAR(cpuPendingIntr);
|
|
|
|
|
Tick intrEventTick;
|
|
|
|
|
UNSERIALIZE_SCALAR(intrEventTick);
|
|
|
|
|
if (intrEventTick) {
|
|
|
|
|
intrEvent = new IntrEvent(this, true);
|
|
|
|
|
intrEvent->schedule(intrEventTick);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
2006-04-25 01:31:50 +02:00
|
|
|
Device::serialize(std::ostream &os)
|
2004-11-13 23:10:48 +01:00
|
|
|
{
|
2006-05-12 23:47:23 +02:00
|
|
|
int count;
|
|
|
|
|
|
2004-11-13 23:10:48 +01:00
|
|
|
// Serialize the PciDev base class
|
|
|
|
|
Base::serialize(os);
|
|
|
|
|
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
if (rxState == rxCopy)
|
|
|
|
|
panic("can't serialize with an in flight dma request rxState=%s",
|
|
|
|
|
RxStateStrings[rxState]);
|
2004-11-13 23:10:48 +01:00
|
|
|
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
if (txState == txCopy)
|
|
|
|
|
panic("can't serialize with an in flight dma request txState=%s",
|
|
|
|
|
TxStateStrings[txState]);
|
2004-11-13 23:10:48 +01:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Serialize the device registers
|
|
|
|
|
*/
|
|
|
|
|
SERIALIZE_SCALAR(regs.Config);
|
|
|
|
|
SERIALIZE_SCALAR(regs.IntrStatus);
|
|
|
|
|
SERIALIZE_SCALAR(regs.IntrMask);
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
SERIALIZE_SCALAR(regs.RxMaxCopy);
|
|
|
|
|
SERIALIZE_SCALAR(regs.TxMaxCopy);
|
|
|
|
|
SERIALIZE_SCALAR(regs.RxMaxIntr);
|
2006-04-26 23:52:33 +02:00
|
|
|
SERIALIZE_SCALAR(regs.VirtualCount);
|
2004-11-13 23:10:48 +01:00
|
|
|
SERIALIZE_SCALAR(regs.RxData);
|
|
|
|
|
SERIALIZE_SCALAR(regs.RxDone);
|
|
|
|
|
SERIALIZE_SCALAR(regs.TxData);
|
|
|
|
|
SERIALIZE_SCALAR(regs.TxDone);
|
|
|
|
|
|
2005-11-25 19:33:36 +01:00
|
|
|
/*
|
|
|
|
|
* Serialize the virtual nic state
|
|
|
|
|
*/
|
|
|
|
|
int virtualRegsSize = virtualRegs.size();
|
|
|
|
|
SERIALIZE_SCALAR(virtualRegsSize);
|
|
|
|
|
for (int i = 0; i < virtualRegsSize; ++i) {
|
|
|
|
|
VirtualReg *vnic = &virtualRegs[i];
|
|
|
|
|
|
2006-04-25 01:31:50 +02:00
|
|
|
std::string reg = csprintf("vnic%d", i);
|
2005-11-25 19:33:36 +01:00
|
|
|
paramOut(os, reg + ".RxData", vnic->RxData);
|
|
|
|
|
paramOut(os, reg + ".RxDone", vnic->RxDone);
|
|
|
|
|
paramOut(os, reg + ".TxData", vnic->TxData);
|
|
|
|
|
paramOut(os, reg + ".TxDone", vnic->TxDone);
|
|
|
|
|
|
|
|
|
|
bool rxPacketExists = vnic->rxPacket != rxFifo.end();
|
|
|
|
|
paramOut(os, reg + ".rxPacketExists", rxPacketExists);
|
|
|
|
|
if (rxPacketExists) {
|
|
|
|
|
int rxPacket = 0;
|
|
|
|
|
PacketFifo::iterator i = rxFifo.begin();
|
|
|
|
|
while (i != vnic->rxPacket) {
|
|
|
|
|
assert(i != rxFifo.end());
|
|
|
|
|
++i;
|
|
|
|
|
++rxPacket;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
paramOut(os, reg + ".rxPacket", rxPacket);
|
|
|
|
|
paramOut(os, reg + ".rxPacketOffset", vnic->rxPacketOffset);
|
|
|
|
|
paramOut(os, reg + ".rxPacketBytes", vnic->rxPacketBytes);
|
|
|
|
|
}
|
|
|
|
|
paramOut(os, reg + ".rxDoneData", vnic->rxDoneData);
|
|
|
|
|
}
|
|
|
|
|
|
2006-04-26 23:52:33 +02:00
|
|
|
int rxFifoPtr = rxFifo.countPacketsBefore(this->rxFifoPtr);
|
|
|
|
|
SERIALIZE_SCALAR(rxFifoPtr);
|
2005-11-25 19:33:36 +01:00
|
|
|
|
2006-04-26 23:52:33 +02:00
|
|
|
SERIALIZE_SCALAR(rxActive);
|
|
|
|
|
|
|
|
|
|
VirtualList::iterator i, end;
|
2005-11-25 19:33:36 +01:00
|
|
|
for (count = 0, i = rxList.begin(), end = rxList.end(); i != end; ++i)
|
|
|
|
|
paramOut(os, csprintf("rxList%d", count++), *i);
|
2006-04-26 23:52:33 +02:00
|
|
|
int rxListSize = count;
|
|
|
|
|
SERIALIZE_SCALAR(rxListSize);
|
|
|
|
|
|
|
|
|
|
for (count = 0, i = rxBusy.begin(), end = rxBusy.end(); i != end; ++i)
|
|
|
|
|
paramOut(os, csprintf("rxBusy%d", count++), *i);
|
|
|
|
|
int rxBusySize = count;
|
|
|
|
|
SERIALIZE_SCALAR(rxBusySize);
|
2005-11-25 19:33:36 +01:00
|
|
|
|
|
|
|
|
for (count = 0, i = txList.begin(), end = txList.end(); i != end; ++i)
|
|
|
|
|
paramOut(os, csprintf("txList%d", count++), *i);
|
2006-04-26 23:52:33 +02:00
|
|
|
int txListSize = count;
|
|
|
|
|
SERIALIZE_SCALAR(txListSize);
|
2005-11-25 19:33:36 +01:00
|
|
|
|
2004-11-13 23:10:48 +01:00
|
|
|
/*
|
|
|
|
|
* Serialize rx state machine
|
|
|
|
|
*/
|
|
|
|
|
int rxState = this->rxState;
|
|
|
|
|
SERIALIZE_SCALAR(rxState);
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
SERIALIZE_SCALAR(rxEmpty);
|
2006-04-26 23:52:33 +02:00
|
|
|
SERIALIZE_SCALAR(rxLow);
|
2004-11-13 23:10:48 +01:00
|
|
|
rxFifo.serialize("rxFifo", os);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Serialize tx state machine
|
|
|
|
|
*/
|
|
|
|
|
int txState = this->txState;
|
|
|
|
|
SERIALIZE_SCALAR(txState);
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
SERIALIZE_SCALAR(txFull);
|
2004-11-13 23:10:48 +01:00
|
|
|
txFifo.serialize("txFifo", os);
|
|
|
|
|
bool txPacketExists = txPacket;
|
|
|
|
|
SERIALIZE_SCALAR(txPacketExists);
|
|
|
|
|
if (txPacketExists) {
|
|
|
|
|
txPacket->serialize("txPacket", os);
|
2005-11-25 19:33:36 +01:00
|
|
|
SERIALIZE_SCALAR(txPacketOffset);
|
|
|
|
|
SERIALIZE_SCALAR(txPacketBytes);
|
2004-11-13 23:10:48 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* If there's a pending transmit, store the time so we can
|
|
|
|
|
* reschedule it later
|
|
|
|
|
*/
|
|
|
|
|
Tick transmitTick = txEvent.scheduled() ? txEvent.when() - curTick : 0;
|
|
|
|
|
SERIALIZE_SCALAR(transmitTick);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
Device::unserialize(Checkpoint *cp, const std::string §ion)
|
|
|
|
|
{
|
|
|
|
|
// Unserialize the PciDev base class
|
|
|
|
|
Base::unserialize(cp, section);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Unserialize the device registers
|
|
|
|
|
*/
|
|
|
|
|
UNSERIALIZE_SCALAR(regs.Config);
|
|
|
|
|
UNSERIALIZE_SCALAR(regs.IntrStatus);
|
|
|
|
|
UNSERIALIZE_SCALAR(regs.IntrMask);
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
UNSERIALIZE_SCALAR(regs.RxMaxCopy);
|
|
|
|
|
UNSERIALIZE_SCALAR(regs.TxMaxCopy);
|
|
|
|
|
UNSERIALIZE_SCALAR(regs.RxMaxIntr);
|
2006-04-26 23:52:33 +02:00
|
|
|
UNSERIALIZE_SCALAR(regs.VirtualCount);
|
2004-11-13 23:10:48 +01:00
|
|
|
UNSERIALIZE_SCALAR(regs.RxData);
|
|
|
|
|
UNSERIALIZE_SCALAR(regs.RxDone);
|
|
|
|
|
UNSERIALIZE_SCALAR(regs.TxData);
|
|
|
|
|
UNSERIALIZE_SCALAR(regs.TxDone);
|
|
|
|
|
|
2006-04-26 23:52:33 +02:00
|
|
|
UNSERIALIZE_SCALAR(rxActive);
|
|
|
|
|
|
2005-11-25 19:33:36 +01:00
|
|
|
int rxListSize;
|
|
|
|
|
UNSERIALIZE_SCALAR(rxListSize);
|
|
|
|
|
rxList.clear();
|
|
|
|
|
for (int i = 0; i < rxListSize; ++i) {
|
|
|
|
|
int value;
|
|
|
|
|
paramIn(cp, section, csprintf("rxList%d", i), value);
|
|
|
|
|
rxList.push_back(value);
|
|
|
|
|
}
|
|
|
|
|
|
2006-04-26 23:52:33 +02:00
|
|
|
int rxBusySize;
|
|
|
|
|
UNSERIALIZE_SCALAR(rxBusySize);
|
|
|
|
|
rxBusy.clear();
|
|
|
|
|
for (int i = 0; i < rxBusySize; ++i) {
|
|
|
|
|
int value;
|
|
|
|
|
paramIn(cp, section, csprintf("rxBusy%d", i), value);
|
|
|
|
|
rxBusy.push_back(value);
|
|
|
|
|
}
|
|
|
|
|
|
2005-11-25 19:33:36 +01:00
|
|
|
int txListSize;
|
|
|
|
|
UNSERIALIZE_SCALAR(txListSize);
|
|
|
|
|
txList.clear();
|
|
|
|
|
for (int i = 0; i < txListSize; ++i) {
|
|
|
|
|
int value;
|
|
|
|
|
paramIn(cp, section, csprintf("txList%d", i), value);
|
|
|
|
|
txList.push_back(value);
|
|
|
|
|
}
|
|
|
|
|
|
2004-11-13 23:10:48 +01:00
|
|
|
/*
|
|
|
|
|
* Unserialize rx state machine
|
|
|
|
|
*/
|
|
|
|
|
int rxState;
|
|
|
|
|
UNSERIALIZE_SCALAR(rxState);
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
UNSERIALIZE_SCALAR(rxEmpty);
|
2006-04-26 23:52:33 +02:00
|
|
|
UNSERIALIZE_SCALAR(rxLow);
|
2004-11-13 23:10:48 +01:00
|
|
|
this->rxState = (RxState) rxState;
|
|
|
|
|
rxFifo.unserialize("rxFifo", cp, section);
|
|
|
|
|
|
2006-04-26 23:52:33 +02:00
|
|
|
int rxFifoPtr;
|
|
|
|
|
UNSERIALIZE_SCALAR(rxFifoPtr);
|
|
|
|
|
this->rxFifoPtr = rxFifo.begin();
|
|
|
|
|
for (int i = 0; i < rxFifoPtr; ++i)
|
|
|
|
|
++this->rxFifoPtr;
|
|
|
|
|
|
2004-11-13 23:10:48 +01:00
|
|
|
/*
|
|
|
|
|
* Unserialize tx state machine
|
|
|
|
|
*/
|
|
|
|
|
int txState;
|
|
|
|
|
UNSERIALIZE_SCALAR(txState);
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
UNSERIALIZE_SCALAR(txFull);
|
2004-11-13 23:10:48 +01:00
|
|
|
this->txState = (TxState) txState;
|
|
|
|
|
txFifo.unserialize("txFifo", cp, section);
|
|
|
|
|
bool txPacketExists;
|
|
|
|
|
UNSERIALIZE_SCALAR(txPacketExists);
|
|
|
|
|
txPacket = 0;
|
|
|
|
|
if (txPacketExists) {
|
2006-04-25 01:31:50 +02:00
|
|
|
txPacket = new EthPacketData(16384);
|
2004-11-13 23:10:48 +01:00
|
|
|
txPacket->unserialize("txPacket", cp, section);
|
2005-11-25 19:33:36 +01:00
|
|
|
UNSERIALIZE_SCALAR(txPacketOffset);
|
|
|
|
|
UNSERIALIZE_SCALAR(txPacketBytes);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* unserialize the virtual nic registers/state
|
|
|
|
|
*
|
|
|
|
|
* this must be done after the unserialization of the rxFifo
|
|
|
|
|
* because the packet iterators depend on the fifo being populated
|
|
|
|
|
*/
|
|
|
|
|
int virtualRegsSize;
|
|
|
|
|
UNSERIALIZE_SCALAR(virtualRegsSize);
|
|
|
|
|
virtualRegs.clear();
|
|
|
|
|
virtualRegs.resize(virtualRegsSize);
|
|
|
|
|
for (int i = 0; i < virtualRegsSize; ++i) {
|
|
|
|
|
VirtualReg *vnic = &virtualRegs[i];
|
2006-04-25 01:31:50 +02:00
|
|
|
std::string reg = csprintf("vnic%d", i);
|
2005-11-25 19:33:36 +01:00
|
|
|
|
|
|
|
|
paramIn(cp, section, reg + ".RxData", vnic->RxData);
|
|
|
|
|
paramIn(cp, section, reg + ".RxDone", vnic->RxDone);
|
|
|
|
|
paramIn(cp, section, reg + ".TxData", vnic->TxData);
|
|
|
|
|
paramIn(cp, section, reg + ".TxDone", vnic->TxDone);
|
|
|
|
|
|
2006-04-26 23:52:33 +02:00
|
|
|
vnic->rxUnique = rxUnique++;
|
|
|
|
|
vnic->txUnique = txUnique++;
|
|
|
|
|
|
2005-11-25 19:33:36 +01:00
|
|
|
bool rxPacketExists;
|
|
|
|
|
paramIn(cp, section, reg + ".rxPacketExists", rxPacketExists);
|
|
|
|
|
if (rxPacketExists) {
|
|
|
|
|
int rxPacket;
|
|
|
|
|
paramIn(cp, section, reg + ".rxPacket", rxPacket);
|
|
|
|
|
vnic->rxPacket = rxFifo.begin();
|
|
|
|
|
while (rxPacket--)
|
|
|
|
|
++vnic->rxPacket;
|
|
|
|
|
|
|
|
|
|
paramIn(cp, section, reg + ".rxPacketOffset",
|
|
|
|
|
vnic->rxPacketOffset);
|
|
|
|
|
paramIn(cp, section, reg + ".rxPacketBytes", vnic->rxPacketBytes);
|
|
|
|
|
} else {
|
|
|
|
|
vnic->rxPacket = rxFifo.end();
|
|
|
|
|
}
|
|
|
|
|
paramIn(cp, section, reg + ".rxDoneData", vnic->rxDoneData);
|
2004-11-13 23:10:48 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* If there's a pending transmit, reschedule it now
|
|
|
|
|
*/
|
|
|
|
|
Tick transmitTick;
|
|
|
|
|
UNSERIALIZE_SCALAR(transmitTick);
|
|
|
|
|
if (transmitTick)
|
|
|
|
|
txEvent.schedule(curTick + transmitTick);
|
|
|
|
|
|
2006-04-25 01:31:50 +02:00
|
|
|
pioPort->sendStatusChange(Port::RangeChange);
|
2004-11-13 23:10:48 +01:00
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
2006-08-15 23:41:22 +02:00
|
|
|
/* namespace Sinic */ }
|
2006-04-25 01:31:50 +02:00
|
|
|
|
2006-08-15 23:41:22 +02:00
|
|
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS_WNS(Sinic, SinicInterface)
|
2004-11-13 23:10:48 +01:00
|
|
|
|
|
|
|
|
SimObjectParam<EtherInt *> peer;
|
2006-08-15 23:41:22 +02:00
|
|
|
SimObjectParam<Sinic::Device *> device;
|
|
|
|
|
END_DECLARE_SIM_OBJECT_PARAMS_WNS(Sinic, SinicInterface)
|
2004-11-13 23:10:48 +01:00
|
|
|
|
2006-08-15 23:41:22 +02:00
|
|
|
BEGIN_INIT_SIM_OBJECT_PARAMS_WNS(Sinic, SinicInterface)
|
2004-11-13 23:10:48 +01:00
|
|
|
|
|
|
|
|
INIT_PARAM_DFLT(peer, "peer interface", NULL),
|
|
|
|
|
INIT_PARAM(device, "Ethernet device of this interface")
|
|
|
|
|
|
2006-08-15 23:41:22 +02:00
|
|
|
END_INIT_SIM_OBJECT_PARAMS_WNS(Sinic, SinicInterface)
|
2004-11-13 23:10:48 +01:00
|
|
|
|
2006-08-15 23:41:22 +02:00
|
|
|
CREATE_SIM_OBJECT_WNS(Sinic, SinicInterface)
|
2004-11-13 23:10:48 +01:00
|
|
|
{
|
2006-08-15 23:41:22 +02:00
|
|
|
Sinic::Interface *dev_int = new Sinic::Interface(getInstanceName(), device);
|
2004-11-13 23:10:48 +01:00
|
|
|
|
|
|
|
|
EtherInt *p = (EtherInt *)peer;
|
|
|
|
|
if (p) {
|
|
|
|
|
dev_int->setPeer(p);
|
|
|
|
|
p->setPeer(dev_int);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return dev_int;
|
|
|
|
|
}
|
|
|
|
|
|
2006-08-15 23:41:22 +02:00
|
|
|
REGISTER_SIM_OBJECT_WNS(Sinic, "SinicInt", SinicInterface)
|
2004-11-13 23:10:48 +01:00
|
|
|
|
|
|
|
|
|
2006-08-15 23:41:22 +02:00
|
|
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS_WNS(Sinic, SinicDevice)
|
2004-11-13 23:10:48 +01:00
|
|
|
|
2005-10-19 04:05:05 +02:00
|
|
|
|
2006-04-25 01:31:50 +02:00
|
|
|
SimObjectParam<System *> system;
|
|
|
|
|
SimObjectParam<Platform *> platform;
|
2004-11-13 23:10:48 +01:00
|
|
|
SimObjectParam<PciConfigData *> configdata;
|
|
|
|
|
Param<uint32_t> pci_bus;
|
|
|
|
|
Param<uint32_t> pci_dev;
|
|
|
|
|
Param<uint32_t> pci_func;
|
2006-04-25 01:31:50 +02:00
|
|
|
Param<Tick> pio_latency;
|
2006-07-27 22:43:02 +02:00
|
|
|
Param<Tick> config_latency;
|
2006-04-25 01:31:50 +02:00
|
|
|
Param<Tick> intr_delay;
|
2005-10-19 04:05:05 +02:00
|
|
|
|
2006-04-25 01:31:50 +02:00
|
|
|
Param<Tick> clock;
|
2005-10-19 04:05:05 +02:00
|
|
|
Param<Tick> dma_read_delay;
|
|
|
|
|
Param<Tick> dma_read_factor;
|
|
|
|
|
Param<Tick> dma_write_delay;
|
|
|
|
|
Param<Tick> dma_write_factor;
|
|
|
|
|
|
|
|
|
|
Param<Tick> rx_delay;
|
|
|
|
|
Param<Tick> tx_delay;
|
2004-11-13 23:10:48 +01:00
|
|
|
Param<uint32_t> rx_max_copy;
|
|
|
|
|
Param<uint32_t> tx_max_copy;
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
Param<uint32_t> rx_max_intr;
|
2004-11-13 23:10:48 +01:00
|
|
|
Param<uint32_t> rx_fifo_size;
|
|
|
|
|
Param<uint32_t> tx_fifo_size;
|
|
|
|
|
Param<uint32_t> rx_fifo_threshold;
|
2006-04-26 23:52:33 +02:00
|
|
|
Param<uint32_t> rx_fifo_low_mark;
|
|
|
|
|
Param<uint32_t> tx_fifo_high_mark;
|
2004-11-13 23:10:48 +01:00
|
|
|
Param<uint32_t> tx_fifo_threshold;
|
2005-10-19 04:05:05 +02:00
|
|
|
|
|
|
|
|
Param<bool> rx_filter;
|
2006-04-25 01:31:50 +02:00
|
|
|
Param<std::string> hardware_address;
|
2005-11-25 19:33:36 +01:00
|
|
|
Param<bool> rx_thread;
|
|
|
|
|
Param<bool> tx_thread;
|
2006-03-03 20:17:48 +01:00
|
|
|
Param<bool> rss;
|
2006-04-26 23:52:33 +02:00
|
|
|
Param<uint32_t> virtual_count;
|
|
|
|
|
Param<bool> zero_copy;
|
|
|
|
|
Param<bool> delay_copy;
|
|
|
|
|
Param<bool> virtual_addr;
|
2004-11-13 23:10:48 +01:00
|
|
|
|
2006-08-15 23:41:22 +02:00
|
|
|
END_DECLARE_SIM_OBJECT_PARAMS_WNS(Sinic, SinicDevice)
|
2004-11-13 23:10:48 +01:00
|
|
|
|
2006-08-15 23:41:22 +02:00
|
|
|
BEGIN_INIT_SIM_OBJECT_PARAMS_WNS(Sinic, SinicDevice)
|
2004-11-13 23:10:48 +01:00
|
|
|
|
2005-10-19 04:05:05 +02:00
|
|
|
|
2006-04-25 01:31:50 +02:00
|
|
|
INIT_PARAM(system, "System pointer"),
|
|
|
|
|
INIT_PARAM(platform, "Platform pointer"),
|
2004-11-13 23:10:48 +01:00
|
|
|
INIT_PARAM(configdata, "PCI Config data"),
|
2006-04-25 01:31:50 +02:00
|
|
|
INIT_PARAM(pci_bus, "PCI bus ID"),
|
2004-11-13 23:10:48 +01:00
|
|
|
INIT_PARAM(pci_dev, "PCI device number"),
|
|
|
|
|
INIT_PARAM(pci_func, "PCI function code"),
|
2006-04-25 01:31:50 +02:00
|
|
|
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
|
2006-07-27 22:43:02 +02:00
|
|
|
INIT_PARAM(config_latency, "Number of cycles for a config read or write"),
|
2006-04-25 01:31:50 +02:00
|
|
|
INIT_PARAM(intr_delay, "Interrupt Delay"),
|
|
|
|
|
INIT_PARAM(clock, "State machine cycle time"),
|
2005-10-19 04:05:05 +02:00
|
|
|
|
|
|
|
|
INIT_PARAM(dma_read_delay, "fixed delay for dma reads"),
|
|
|
|
|
INIT_PARAM(dma_read_factor, "multiplier for dma reads"),
|
|
|
|
|
INIT_PARAM(dma_write_delay, "fixed delay for dma writes"),
|
|
|
|
|
INIT_PARAM(dma_write_factor, "multiplier for dma writes"),
|
|
|
|
|
|
|
|
|
|
INIT_PARAM(rx_delay, "Receive Delay"),
|
|
|
|
|
INIT_PARAM(tx_delay, "Transmit Delay"),
|
|
|
|
|
INIT_PARAM(rx_max_copy, "rx max copy"),
|
|
|
|
|
INIT_PARAM(tx_max_copy, "rx max copy"),
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
INIT_PARAM(rx_max_intr, "rx max intr"),
|
2005-10-19 04:05:05 +02:00
|
|
|
INIT_PARAM(rx_fifo_size, "max size in bytes of rxFifo"),
|
|
|
|
|
INIT_PARAM(tx_fifo_size, "max size in bytes of txFifo"),
|
|
|
|
|
INIT_PARAM(rx_fifo_threshold, "max size in bytes of rxFifo"),
|
2006-04-26 23:52:33 +02:00
|
|
|
INIT_PARAM(rx_fifo_low_mark, "max size in bytes of rxFifo"),
|
|
|
|
|
INIT_PARAM(tx_fifo_high_mark, "max size in bytes of txFifo"),
|
2005-10-19 04:05:05 +02:00
|
|
|
INIT_PARAM(tx_fifo_threshold, "max size in bytes of txFifo"),
|
|
|
|
|
|
|
|
|
|
INIT_PARAM(rx_filter, "Enable Receive Filter"),
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
INIT_PARAM(hardware_address, "Ethernet Hardware Address"),
|
2005-11-25 19:33:36 +01:00
|
|
|
INIT_PARAM(rx_thread, ""),
|
2006-03-03 20:17:48 +01:00
|
|
|
INIT_PARAM(tx_thread, ""),
|
2006-04-26 23:52:33 +02:00
|
|
|
INIT_PARAM(rss, ""),
|
|
|
|
|
INIT_PARAM(virtual_count, ""),
|
|
|
|
|
INIT_PARAM(zero_copy, ""),
|
|
|
|
|
INIT_PARAM(delay_copy, ""),
|
|
|
|
|
INIT_PARAM(virtual_addr, "")
|
2004-11-13 23:10:48 +01:00
|
|
|
|
2006-08-15 23:41:22 +02:00
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END_INIT_SIM_OBJECT_PARAMS_WNS(Sinic, SinicDevice)
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2004-11-13 23:10:48 +01:00
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2006-08-15 23:41:22 +02:00
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CREATE_SIM_OBJECT_WNS(Sinic, SinicDevice)
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2004-11-13 23:10:48 +01:00
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{
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2006-08-15 23:41:22 +02:00
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Sinic::Sinic::Device::Params *params = new Device::Params;
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2004-11-13 23:10:48 +01:00
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params->name = getInstanceName();
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2006-04-25 01:31:50 +02:00
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params->platform = platform;
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params->system = system;
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2004-11-13 23:10:48 +01:00
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params->configData = configdata;
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params->busNum = pci_bus;
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params->deviceNum = pci_dev;
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params->functionNum = pci_func;
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2006-04-25 01:31:50 +02:00
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params->pio_delay = pio_latency;
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2006-07-27 22:43:02 +02:00
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params->config_delay = config_latency;
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2006-04-25 01:31:50 +02:00
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params->intr_delay = intr_delay;
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params->clock = clock;
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2005-10-19 04:05:05 +02:00
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params->dma_read_delay = dma_read_delay;
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params->dma_read_factor = dma_read_factor;
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params->dma_write_delay = dma_write_delay;
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params->dma_write_factor = dma_write_factor;
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params->tx_delay = tx_delay;
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params->rx_delay = rx_delay;
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2004-11-13 23:10:48 +01:00
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params->rx_max_copy = rx_max_copy;
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params->tx_max_copy = tx_max_copy;
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
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params->rx_max_intr = rx_max_intr;
|
2004-11-13 23:10:48 +01:00
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params->rx_fifo_size = rx_fifo_size;
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params->tx_fifo_size = tx_fifo_size;
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params->rx_fifo_threshold = rx_fifo_threshold;
|
2006-04-26 23:52:33 +02:00
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params->rx_fifo_low_mark = rx_fifo_low_mark;
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params->tx_fifo_high_mark = tx_fifo_high_mark;
|
2004-11-13 23:10:48 +01:00
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params->tx_fifo_threshold = tx_fifo_threshold;
|
2005-10-19 04:05:05 +02:00
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params->rx_filter = rx_filter;
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params->eaddr = hardware_address;
|
2005-11-25 19:33:36 +01:00
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params->rx_thread = rx_thread;
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params->tx_thread = tx_thread;
|
2006-03-03 20:17:48 +01:00
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params->rss = rss;
|
2006-04-26 23:52:33 +02:00
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params->virtual_count = virtual_count;
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params->zero_copy = zero_copy;
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params->delay_copy = delay_copy;
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params->virtual_addr = virtual_addr;
|
2005-10-19 04:05:05 +02:00
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|
2006-08-15 23:41:22 +02:00
|
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|
return new Sinic::Device(params);
|
2004-11-13 23:10:48 +01:00
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}
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2006-08-15 23:41:22 +02:00
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REGISTER_SIM_OBJECT_WNS(Sinic, "Sinic", SinicDevice)
|
2004-11-13 23:10:48 +01:00
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