2010-07-27 07:03:44 +02:00
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---------- Begin Simulation Statistics ----------
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2011-03-18 01:20:22 +01:00
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sim_seconds 0.722234 # Number of seconds simulated
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sim_ticks 722234364000 # Number of ticks simulated
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2012-01-25 18:19:50 +01:00
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final_tick 722234364000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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2012-03-09 21:33:07 +01:00
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host_inst_rate 1812748 # Simulator instruction rate (inst/s)
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host_op_rate 2042661 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 2592600297 # Simulator tick rate (ticks/s)
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host_mem_usage 228776 # Number of bytes of host memory used
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host_seconds 278.58 # Real time elapsed on the host
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2012-02-12 23:07:43 +01:00
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sim_insts 504986861 # Number of instructions simulated
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sim_ops 569034848 # Number of ops (including micro ops) simulated
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2012-01-25 18:19:50 +01:00
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system.physmem.bytes_read 14797056 # Number of bytes read from this memory
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system.physmem.bytes_inst_read 188608 # Number of instructions bytes read from this memory
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system.physmem.bytes_written 11027328 # Number of bytes written to this memory
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system.physmem.num_reads 231204 # Number of read requests responded to by this memory
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system.physmem.num_writes 172302 # Number of write requests responded to by this memory
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system.physmem.num_other 0 # Number of other requests responded to by this memory
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system.physmem.bw_read 20487887 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read 261145 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write 15268351 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total 35756238 # Total bandwidth to/from this memory (bytes/s)
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2010-11-08 20:59:35 +01:00
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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2010-07-27 07:03:44 +02:00
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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2012-01-25 18:19:50 +01:00
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 548 # Number of system calls
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system.cpu.numCycles 1444468728 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2012-02-12 23:07:43 +01:00
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system.cpu.committedInsts 504986861 # Number of instructions committed
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system.cpu.committedOps 569034848 # Number of ops (including micro ops) committed
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2012-01-25 18:19:50 +01:00
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system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
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system.cpu.num_func_calls 15725605 # number of times a function call or return occured
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2012-03-09 21:33:07 +01:00
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system.cpu.num_conditional_control_insts 98480815 # number of instructions that are conditional controls
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2012-01-25 18:19:50 +01:00
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system.cpu.num_int_insts 470727703 # number of integer instructions
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system.cpu.num_fp_insts 16 # number of float instructions
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system.cpu.num_int_register_reads 2844375220 # number of times the integer registers were read
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system.cpu.num_int_register_writes 646169365 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
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system.cpu.num_mem_refs 182890035 # number of memory refs
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system.cpu.num_load_insts 126029556 # Number of load instructions
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system.cpu.num_store_insts 56860479 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 1444468728 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.replacements 9788 # number of replacements
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system.cpu.icache.tagsinuse 984.426148 # Cycle average of tags in use
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system.cpu.icache.total_refs 516599864 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 44839.845847 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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2012-02-12 23:07:43 +01:00
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system.cpu.icache.occ_blocks::cpu.inst 984.426148 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::cpu.inst 0.480677 # Average percentage of cache occupancy
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system.cpu.icache.occ_percent::total 0.480677 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::cpu.inst 516599864 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 516599864 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 516599864 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 516599864 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 516599864 # number of overall hits
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system.cpu.icache.overall_hits::total 516599864 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 11521 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 11521 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 11521 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses
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system.cpu.icache.overall_misses::total 11521 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 285068000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 285068000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 285068000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 285068000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 285068000 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 285068000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 516611385 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 516611385 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 516611385 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 516611385 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::cpu.inst 516611385 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 516611385 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24743.338252 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 24743.338252 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 24743.338252 # average overall miss latency
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2010-07-27 07:03:44 +02:00
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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2012-01-25 18:19:50 +01:00
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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2010-07-27 07:03:44 +02:00
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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2012-02-12 23:07:43 +01:00
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11521 # number of ReadReq MSHR misses
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system.cpu.icache.ReadReq_mshr_misses::total 11521 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::cpu.inst 11521 # number of demand (read+write) MSHR misses
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system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 250505000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_latency::total 250505000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::cpu.inst 250505000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::total 250505000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::cpu.inst 250505000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 250505000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21743.338252 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21743.338252 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21743.338252 # average overall mshr miss latency
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2012-01-25 18:19:50 +01:00
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.replacements 1134822 # number of replacements
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system.cpu.dcache.tagsinuse 4065.490059 # Cycle average of tags in use
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system.cpu.dcache.total_refs 179817787 # Total number of references to valid blocks.
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system.cpu.dcache.sampled_refs 1138918 # Sample count of references to valid blocks.
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system.cpu.dcache.avg_refs 157.884753 # Average number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 11889987000 # Cycle when the warmup percentage was hit.
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2012-02-12 23:07:43 +01:00
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system.cpu.dcache.occ_blocks::cpu.data 4065.490059 # Average occupied blocks per requestor
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system.cpu.dcache.occ_percent::cpu.data 0.992551 # Average percentage of cache occupancy
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system.cpu.dcache.occ_percent::total 0.992551 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits::cpu.data 122957659 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 122957659 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits
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system.cpu.dcache.WriteReq_hits::total 53883046 # number of WriteReq hits
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system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits
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system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits
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system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
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system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
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system.cpu.dcache.demand_hits::cpu.data 176840705 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits::total 176840705 # number of demand (read+write) hits
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system.cpu.dcache.overall_hits::cpu.data 176840705 # number of overall hits
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system.cpu.dcache.overall_hits::total 176840705 # number of overall hits
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system.cpu.dcache.ReadReq_misses::cpu.data 782658 # number of ReadReq misses
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system.cpu.dcache.ReadReq_misses::total 782658 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses::total 356260 # number of WriteReq misses
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system.cpu.dcache.demand_misses::cpu.data 1138918 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses::total 1138918 # number of demand (read+write) misses
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system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses
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system.cpu.dcache.overall_misses::total 1138918 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency::cpu.data 15502704000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_latency::total 15502704000 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::cpu.data 10028942000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::total 10028942000 # number of WriteReq miss cycles
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system.cpu.dcache.demand_miss_latency::cpu.data 25531646000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_latency::total 25531646000 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency::cpu.data 25531646000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_latency::total 25531646000 # number of overall miss cycles
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system.cpu.dcache.ReadReq_accesses::cpu.data 123740317 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_accesses::total 123740317 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
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|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses::cpu.data 177979623 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_accesses::total 177979623 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::cpu.data 177979623 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::total 177979623 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006325 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.006399 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.006399 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19807.762778 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28150.625947 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22417.457622 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22417.457622 # average overall miss latency
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.writebacks::writebacks 1025440 # number of writebacks
|
|
|
|
|
system.cpu.dcache.writebacks::total 1025440 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782658 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 782658 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 356260 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 1138918 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::total 1138918 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13154730000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 13154730000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8960162000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8960162000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22114892000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 22114892000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22114892000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 22114892000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006325 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16807.762778 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25150.625947 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19417.457622 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19417.457622 # average overall mshr miss latency
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.l2cache.replacements 212089 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 20443.163614 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 1426644 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 232128 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 6.145937 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 513135223000 # Cycle when the warmup percentage was hit.
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.occ_blocks::writebacks 14594.006011 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 132.842413 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_blocks::cpu.data 5716.315189 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_percent::writebacks 0.445374 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.004054 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.174448 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::total 0.623876 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 8574 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 674432 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::total 683006 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::writebacks 1025440 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::total 1025440 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 236229 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::total 236229 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.inst 8574 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.data 910661 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::total 919235 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.inst 8574 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.data 910661 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::total 919235 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 2947 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 108226 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::total 111173 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 120031 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::total 120031 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.inst 2947 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.data 228257 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::total 231204 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.inst 2947 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.data 228257 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::total 231204 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 153244000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5627752000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 5780996000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6241612000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 6241612000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 153244000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 11869364000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::total 12022608000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 153244000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 11869364000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::total 12022608000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 11521 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 782658 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::total 794179 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 1025440 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::total 1025440 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 356260 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::total 356260 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 11521 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1138918 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::total 1150439 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 11521 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1138918 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::total 1150439 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.255794 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.138280 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.336920 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.255794 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.200416 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.255794 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.200416 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
2010-07-27 07:03:44 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2010-07-27 07:03:44 +02:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.writebacks::writebacks 172302 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.writebacks::total 172302 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2947 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 108226 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 111173 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 120031 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 120031 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2947 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 228257 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::total 231204 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2947 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 228257 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::total 231204 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117880000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4329040000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 4446920000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4801240000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4801240000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117880000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9130280000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 9248160000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117880000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9130280000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 9248160000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.138280 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.336920 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200416 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200416 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2010-07-27 07:03:44 +02:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
