gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.332330                       # Number of seconds simulated
sim_ticks                                2332330037000                       # Number of ticks simulated
final_tick                               2332330037000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1988795                       # Simulator instruction rate (inst/s)
host_op_rate                                  2567201                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            78099767101                       # Simulator tick rate (ticks/s)
host_mem_usage                                 382744                       # Number of bytes of host memory used
host_seconds                                    29.86                       # Real time elapsed on the host
sim_insts                                    59392246                       # Number of instructions simulated
sim_ops                                      76665494                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd    111673344                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker          320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          192                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst            704992                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9071568                       # Number of bytes read from this memory
system.physmem.bytes_read::total            121450416                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       704992                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          704992                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      3703040                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data        3015816                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6718856                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd      13959168                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker            5                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            3                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              17218                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             141777                       # Number of read requests responded to by this memory
system.physmem.num_reads::total              14118171                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           57860                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data            753954                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               811814                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        47880592                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker            137                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             82                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               302269                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              3889487                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                52072569                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          302269                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             302269                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1587700                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data             1293049                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2880748                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1587700                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       47880592                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker           137                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            82                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              302269                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             5182536                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               54953317                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read::cpu.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst             9                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                9                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst            9                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            9                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst            9                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               9                       # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements                         62240                       # number of replacements
system.l2c.tagsinuse                     50004.786190                       # Cycle average of tags in use
system.l2c.total_refs                         1717775                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        127625                       # Sample count of references to valid blocks.
system.l2c.avg_refs                         13.459549                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                  2316513323500                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks        36897.037256                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.dtb.walker        2.960071                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.itb.walker        0.993930                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.inst           7014.608709                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.data           6089.186223                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.563004                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.dtb.walker       0.000045                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.itb.walker       0.000015                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.inst             0.107034                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.data             0.092914                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.763012                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu.dtb.walker          7534                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.itb.walker          3151                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.inst              838895                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.data              364444                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1214024                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          642748                       # number of Writeback hits
system.l2c.Writeback_hits::total               642748                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu.data               26                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  26                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu.data            113737                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               113737                       # number of ReadExReq hits
system.l2c.demand_hits::cpu.dtb.walker           7534                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu.itb.walker           3151                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu.inst               838895                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu.data               478181                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1327761                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu.dtb.walker          7534                       # number of overall hits
system.l2c.overall_hits::cpu.itb.walker          3151                       # number of overall hits
system.l2c.overall_hits::cpu.inst              838895                       # number of overall hits
system.l2c.overall_hits::cpu.data              478181                       # number of overall hits
system.l2c.overall_hits::total                1327761                       # number of overall hits
system.l2c.ReadReq_misses::cpu.dtb.walker            5                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.itb.walker            3                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.inst             10602                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.data              9870                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                20480                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu.data           2918                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              2918                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu.data          133469                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             133469                       # number of ReadExReq misses
system.l2c.demand_misses::cpu.dtb.walker            5                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu.itb.walker            3                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu.inst              10602                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu.data             143339                       # number of demand (read+write) misses
system.l2c.demand_misses::total                153949                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu.dtb.walker            5                       # number of overall misses
system.l2c.overall_misses::cpu.itb.walker            3                       # number of overall misses
system.l2c.overall_misses::cpu.inst             10602                       # number of overall misses
system.l2c.overall_misses::cpu.data            143339                       # number of overall misses
system.l2c.overall_misses::total               153949                       # number of overall misses
system.l2c.ReadReq_accesses::cpu.dtb.walker         7539                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.itb.walker         3154                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.inst          849497                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.data          374314                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1234504                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       642748                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           642748                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu.data         2944                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            2944                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu.data        247206                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           247206                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu.dtb.walker         7539                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.itb.walker         3154                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.inst           849497                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.data           621520                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1481710                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu.dtb.walker         7539                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.itb.walker         3154                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.inst          849497                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.data          621520                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1481710                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.000663                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.000951                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.inst       0.012480                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.data       0.026368                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.016590                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu.data     0.991168                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.991168                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu.data     0.539910                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.539910                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu.dtb.walker     0.000663                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.itb.walker     0.000951                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.inst        0.012480                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.data        0.230627                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.103900                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu.dtb.walker     0.000663                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.itb.walker     0.000951                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.inst       0.012480                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.data       0.230627                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.103900                       # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               57860                       # number of writebacks
system.l2c.writebacks::total                    57860                       # number of writebacks
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                     14971229                       # DTB read hits
system.cpu.dtb.read_misses                       7293                       # DTB read misses
system.cpu.dtb.write_hits                    11217018                       # DTB write hits
system.cpu.dtb.write_misses                      2181                       # DTB write misses
system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                     3492                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                    174                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                       452                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                 14978522                       # DTB read accesses
system.cpu.dtb.write_accesses                11219199                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                          26188247                       # DTB hits
system.cpu.dtb.misses                            9474                       # DTB misses
system.cpu.dtb.accesses                      26197721                       # DTB accesses
system.cpu.itb.inst_hits                     60403303                       # ITB inst hits
system.cpu.itb.inst_misses                       4471                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            2                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                     2343                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                 60407774                       # ITB inst accesses
system.cpu.itb.hits                          60403303                       # DTB hits
system.cpu.itb.misses                            4471                       # DTB misses
system.cpu.itb.accesses                      60407774                       # DTB accesses
system.cpu.numCycles                       4664583062                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                    59392246                       # Number of instructions committed
system.cpu.committedOps                      76665494                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses              68281415                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                  10269                       # Number of float alu accesses
system.cpu.num_func_calls                     2136013                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts      7647793                       # number of instructions that are conditional controls
system.cpu.num_int_insts                     68281415                       # number of integer instructions
system.cpu.num_fp_insts                         10269                       # number of float instructions
system.cpu.num_int_register_reads           345981857                       # number of times the integer registers were read
system.cpu.num_int_register_writes           73062916                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                 7493                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                2780                       # number of times the floating registers were written
system.cpu.num_mem_refs                      27361692                       # number of memory refs
system.cpu.num_load_insts                    15639569                       # Number of load instructions
system.cpu.num_store_insts                   11722123                       # Number of store instructions
system.cpu.num_idle_cycles               4586814358.980880                       # Number of idle cycles
system.cpu.num_busy_cycles               77768703.019120                       # Number of busy cycles
system.cpu.not_idle_fraction                 0.016672                       # Percentage of non-idle cycles
system.cpu.idle_fraction                     0.983328                       # Percentage of idle cycles
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                    82795                       # number of quiesce instructions executed
system.cpu.icache.replacements                 850612                       # number of replacements
system.cpu.icache.tagsinuse                511.678549                       # Cycle average of tags in use
system.cpu.icache.total_refs                 59554939                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                 851124                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                  69.972106                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle             5708999000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     511.678549                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.999372                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.999372                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst     59554939                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        59554939                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      59554939                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         59554939                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     59554939                       # number of overall hits
system.cpu.icache.overall_hits::total        59554939                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       851124                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        851124                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       851124                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         851124                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       851124                       # number of overall misses
system.cpu.icache.overall_misses::total        851124                       # number of overall misses
system.cpu.icache.ReadReq_accesses::cpu.inst     60406063                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     60406063                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     60406063                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     60406063                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     60406063                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     60406063                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014090                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.014090                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.014090                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.014090                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.014090                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.014090                       # miss rate for overall accesses
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.writebacks::writebacks        50093                       # number of writebacks
system.cpu.icache.writebacks::total             50093                       # number of writebacks
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                 623347                       # number of replacements
system.cpu.dcache.tagsinuse                511.997030                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 23628362                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                 623859                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  37.874523                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle               21763000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data     511.997030                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999994                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999994                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     13180074                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        13180074                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      9962087                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        9962087                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       236035                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       236035                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       247222                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       247222                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      23142161                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         23142161                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     23142161                       # number of overall hits
system.cpu.dcache.overall_hits::total        23142161                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       365465                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        365465                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       250150                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       250150                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        11188                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        11188                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data       615615                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total         615615                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data       615615                       # number of overall misses
system.cpu.dcache.overall_misses::total        615615                       # number of overall misses
system.cpu.dcache.ReadReq_accesses::cpu.data     13545539                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     13545539                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     10212237                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     10212237                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       247223                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       247223                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       247222                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       247222                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     23757776                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     23757776                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     23757776                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     23757776                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.026980                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.026980                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.024495                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.024495                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.045255                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.045255                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.025912                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.025912                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.025912                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.025912                       # miss rate for overall accesses
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       592655                       # number of writebacks
system.cpu.dcache.writebacks::total            592655                       # number of writebacks
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.iocache.replacements                         0                       # number of replacements
system.iocache.tagsinuse                            0                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
system.iocache.avg_refs                           nan                       # Average number of references to valid blocks.
system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------