2011-02-07 10:23:16 +01:00
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|
---------- Begin Simulation Statistics ----------
|
2012-01-10 16:59:01 +01:00
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|
|
sim_seconds 5.112043 # Number of seconds simulated
|
|
|
|
|
sim_ticks 5112043255000 # Number of ticks simulated
|
2012-01-25 18:19:50 +01:00
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|
|
final_tick 5112043255000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
2011-02-07 10:23:16 +01:00
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|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
2012-05-09 20:52:14 +02:00
|
|
|
host_inst_rate 720353 # Simulator instruction rate (inst/s)
|
|
|
|
|
host_op_rate 1474974 # Simulator op (including micro ops) rate (op/s)
|
|
|
|
|
host_tick_rate 18429520570 # Simulator tick rate (ticks/s)
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|
|
|
|
host_mem_usage 355156 # Number of bytes of host memory used
|
|
|
|
|
host_seconds 277.38 # Real time elapsed on the host
|
2012-02-12 23:07:43 +01:00
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|
|
sim_insts 199813913 # Number of instructions simulated
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|
|
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|
sim_ops 409133277 # Number of ops (including micro ops) simulated
|
2012-01-25 18:19:50 +01:00
|
|
|
system.physmem.bytes_read 15568704 # Number of bytes read from this memory
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|
|
|
|
system.physmem.bytes_inst_read 972736 # Number of instructions bytes read from this memory
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|
|
|
|
system.physmem.bytes_written 12232896 # Number of bytes written to this memory
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|
|
|
|
system.physmem.num_reads 243261 # Number of read requests responded to by this memory
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|
|
|
|
system.physmem.num_writes 191139 # Number of write requests responded to by this memory
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|
|
|
|
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
|
|
|
|
system.physmem.bw_read 3045495 # Total read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_inst_read 190283 # Instruction read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_write 2392956 # Write bandwidth from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_total 5438452 # Total bandwidth to/from this memory (bytes/s)
|
2012-01-10 16:59:01 +01:00
|
|
|
system.l2c.replacements 164044 # number of replacements
|
|
|
|
|
system.l2c.tagsinuse 36842.944085 # Cycle average of tags in use
|
|
|
|
|
system.l2c.total_refs 3332458 # Total number of references to valid blocks.
|
|
|
|
|
system.l2c.sampled_refs 196390 # Sample count of references to valid blocks.
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|
|
|
|
system.l2c.avg_refs 16.968573 # Average number of references to valid blocks.
|
2011-11-05 21:32:23 +01:00
|
|
|
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2012-02-12 23:07:43 +01:00
|
|
|
system.l2c.occ_blocks::writebacks 27139.322665 # Average occupied blocks per requestor
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|
|
|
|
system.l2c.occ_blocks::cpu.dtb.walker 2.054559 # Average occupied blocks per requestor
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|
|
|
|
system.l2c.occ_blocks::cpu.itb.walker 0.003581 # Average occupied blocks per requestor
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|
|
|
|
system.l2c.occ_blocks::cpu.inst 1828.819855 # Average occupied blocks per requestor
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|
|
|
|
system.l2c.occ_blocks::cpu.data 7872.743425 # Average occupied blocks per requestor
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|
|
|
|
system.l2c.occ_percent::writebacks 0.414113 # Average percentage of cache occupancy
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|
|
|
system.l2c.occ_percent::cpu.dtb.walker 0.000031 # Average percentage of cache occupancy
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|
|
|
|
system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
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|
|
|
|
system.l2c.occ_percent::cpu.inst 0.027906 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.occ_percent::cpu.data 0.120129 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.occ_percent::total 0.562179 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.ReadReq_hits::cpu.dtb.walker 6729 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::cpu.itb.walker 2809 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::cpu.inst 776101 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::cpu.data 1266816 # number of ReadReq hits
|
2012-01-10 16:59:01 +01:00
|
|
|
system.l2c.ReadReq_hits::total 2052455 # number of ReadReq hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.l2c.Writeback_hits::writebacks 1529403 # number of Writeback hits
|
2012-01-10 16:59:01 +01:00
|
|
|
system.l2c.Writeback_hits::total 1529403 # number of Writeback hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.l2c.UpgradeReq_hits::cpu.data 31 # number of UpgradeReq hits
|
2012-01-10 16:59:01 +01:00
|
|
|
system.l2c.UpgradeReq_hits::total 31 # number of UpgradeReq hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.l2c.ReadExReq_hits::cpu.data 168948 # number of ReadExReq hits
|
2012-01-10 16:59:01 +01:00
|
|
|
system.l2c.ReadExReq_hits::total 168948 # number of ReadExReq hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.l2c.demand_hits::cpu.dtb.walker 6729 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::cpu.itb.walker 2809 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::cpu.inst 776101 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::cpu.data 1435764 # number of demand (read+write) hits
|
2012-01-10 16:59:01 +01:00
|
|
|
system.l2c.demand_hits::total 2221403 # number of demand (read+write) hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.l2c.overall_hits::cpu.dtb.walker 6729 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::cpu.itb.walker 2809 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::cpu.inst 776101 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::cpu.data 1435764 # number of overall hits
|
2012-01-10 16:59:01 +01:00
|
|
|
system.l2c.overall_hits::total 2221403 # number of overall hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.l2c.ReadReq_misses::cpu.dtb.walker 16 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_misses::cpu.itb.walker 11 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_misses::cpu.inst 15200 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_misses::cpu.data 40772 # number of ReadReq misses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.l2c.ReadReq_misses::total 55999 # number of ReadReq misses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.l2c.UpgradeReq_misses::cpu.data 1792 # number of UpgradeReq misses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.l2c.UpgradeReq_misses::total 1792 # number of UpgradeReq misses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.l2c.ReadExReq_misses::cpu.data 144639 # number of ReadExReq misses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.l2c.ReadExReq_misses::total 144639 # number of ReadExReq misses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.l2c.demand_misses::cpu.dtb.walker 16 # number of demand (read+write) misses
|
|
|
|
|
system.l2c.demand_misses::cpu.itb.walker 11 # number of demand (read+write) misses
|
|
|
|
|
system.l2c.demand_misses::cpu.inst 15200 # number of demand (read+write) misses
|
|
|
|
|
system.l2c.demand_misses::cpu.data 185411 # number of demand (read+write) misses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.l2c.demand_misses::total 200638 # number of demand (read+write) misses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.l2c.overall_misses::cpu.dtb.walker 16 # number of overall misses
|
|
|
|
|
system.l2c.overall_misses::cpu.itb.walker 11 # number of overall misses
|
|
|
|
|
system.l2c.overall_misses::cpu.inst 15200 # number of overall misses
|
|
|
|
|
system.l2c.overall_misses::cpu.data 185411 # number of overall misses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.l2c.overall_misses::total 200638 # number of overall misses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.l2c.ReadReq_accesses::cpu.dtb.walker 6745 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::cpu.itb.walker 2820 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::cpu.inst 791301 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::cpu.data 1307588 # number of ReadReq accesses(hits+misses)
|
2012-01-10 16:59:01 +01:00
|
|
|
system.l2c.ReadReq_accesses::total 2108454 # number of ReadReq accesses(hits+misses)
|
2012-02-12 23:07:43 +01:00
|
|
|
system.l2c.Writeback_accesses::writebacks 1529403 # number of Writeback accesses(hits+misses)
|
2012-01-10 16:59:01 +01:00
|
|
|
system.l2c.Writeback_accesses::total 1529403 # number of Writeback accesses(hits+misses)
|
2012-02-12 23:07:43 +01:00
|
|
|
system.l2c.UpgradeReq_accesses::cpu.data 1823 # number of UpgradeReq accesses(hits+misses)
|
2012-01-10 16:59:01 +01:00
|
|
|
system.l2c.UpgradeReq_accesses::total 1823 # number of UpgradeReq accesses(hits+misses)
|
2012-02-12 23:07:43 +01:00
|
|
|
system.l2c.ReadExReq_accesses::cpu.data 313587 # number of ReadExReq accesses(hits+misses)
|
2012-01-10 16:59:01 +01:00
|
|
|
system.l2c.ReadExReq_accesses::total 313587 # number of ReadExReq accesses(hits+misses)
|
2012-02-12 23:07:43 +01:00
|
|
|
system.l2c.demand_accesses::cpu.dtb.walker 6745 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::cpu.itb.walker 2820 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::cpu.inst 791301 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::cpu.data 1621175 # number of demand (read+write) accesses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.l2c.demand_accesses::total 2422041 # number of demand (read+write) accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.l2c.overall_accesses::cpu.dtb.walker 6745 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::cpu.itb.walker 2820 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::cpu.inst 791301 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::cpu.data 1621175 # number of overall (read+write) accesses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.l2c.overall_accesses::total 2422041 # number of overall (read+write) accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.002372 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.003901 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::cpu.inst 0.019209 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::cpu.data 0.031181 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_miss_rate::cpu.data 0.982995 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.ReadExReq_miss_rate::cpu.data 0.461240 # miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.demand_miss_rate::cpu.dtb.walker 0.002372 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_miss_rate::cpu.itb.walker 0.003901 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_miss_rate::cpu.inst 0.019209 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_miss_rate::cpu.data 0.114368 # miss rate for demand accesses
|
|
|
|
|
system.l2c.overall_miss_rate::cpu.dtb.walker 0.002372 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_miss_rate::cpu.itb.walker 0.003901 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_miss_rate::cpu.inst 0.019209 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_miss_rate::cpu.data 0.114368 # miss rate for overall accesses
|
2011-11-05 21:32:23 +01:00
|
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-11-05 21:32:23 +01:00
|
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
2012-02-12 23:07:43 +01:00
|
|
|
system.l2c.writebacks::writebacks 144472 # number of writebacks
|
|
|
|
|
system.l2c.writebacks::total 144472 # number of writebacks
|
2011-11-05 21:32:23 +01:00
|
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
2012-01-10 16:59:01 +01:00
|
|
|
system.iocache.replacements 47570 # number of replacements
|
|
|
|
|
system.iocache.tagsinuse 0.042409 # Cycle average of tags in use
|
2011-11-05 21:32:23 +01:00
|
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
2012-01-10 16:59:01 +01:00
|
|
|
system.iocache.sampled_refs 47586 # Sample count of references to valid blocks.
|
2011-02-07 10:23:16 +01:00
|
|
|
system.iocache.avg_refs 0 # Average number of references to valid blocks.
|
2012-01-10 16:59:01 +01:00
|
|
|
system.iocache.warmup_cycle 4994776740009 # Cycle when the warmup percentage was hit.
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.occ_blocks::pc.south_bridge.ide 0.042409 # Average occupied blocks per requestor
|
|
|
|
|
system.iocache.occ_percent::pc.south_bridge.ide 0.002651 # Average percentage of cache occupancy
|
|
|
|
|
system.iocache.occ_percent::total 0.002651 # Average percentage of cache occupancy
|
|
|
|
|
system.iocache.ReadReq_misses::pc.south_bridge.ide 905 # number of ReadReq misses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.iocache.ReadReq_misses::total 905 # number of ReadReq misses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
|
2011-11-05 21:32:23 +01:00
|
|
|
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.demand_misses::pc.south_bridge.ide 47625 # number of demand (read+write) misses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.iocache.demand_misses::total 47625 # number of demand (read+write) misses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.overall_misses::pc.south_bridge.ide 47625 # number of overall misses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.iocache.overall_misses::total 47625 # number of overall misses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.ReadReq_accesses::pc.south_bridge.ide 905 # number of ReadReq accesses(hits+misses)
|
2012-01-10 16:59:01 +01:00
|
|
|
system.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses)
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
|
2011-11-05 21:32:23 +01:00
|
|
|
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.demand_accesses::pc.south_bridge.ide 47625 # number of demand (read+write) accesses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.iocache.demand_accesses::total 47625 # number of demand (read+write) accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.overall_accesses::pc.south_bridge.ide 47625 # number of overall (read+write) accesses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.iocache.overall_accesses::total 47625 # number of overall (read+write) accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
|
|
|
|
|
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
|
|
|
|
|
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
|
|
|
|
|
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
|
2011-11-05 21:32:23 +01:00
|
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-11-05 21:32:23 +01:00
|
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.writebacks::writebacks 46667 # number of writebacks
|
|
|
|
|
system.iocache.writebacks::total 46667 # number of writebacks
|
2011-11-05 21:32:23 +01:00
|
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-02-07 10:23:16 +01:00
|
|
|
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
2011-11-05 21:32:23 +01:00
|
|
|
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
|
2011-02-07 10:23:16 +01:00
|
|
|
system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
|
|
|
|
|
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
|
2011-11-05 21:32:23 +01:00
|
|
|
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
|
2011-02-07 10:23:16 +01:00
|
|
|
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
|
|
|
|
|
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
2011-11-05 21:32:23 +01:00
|
|
|
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
2011-02-07 10:23:16 +01:00
|
|
|
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
|
|
|
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
|
2011-11-05 21:32:23 +01:00
|
|
|
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
|
2011-02-07 10:23:16 +01:00
|
|
|
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.numCycles 10224086531 # number of cpu cycles simulated
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
|
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.committedInsts 199813913 # Number of instructions committed
|
|
|
|
|
system.cpu.committedOps 409133277 # Number of ops (including micro ops) committed
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.num_int_alu_accesses 374297244 # Number of integer alu accesses
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
|
|
|
|
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.num_conditional_control_insts 39954968 # number of instructions that are conditional controls
|
|
|
|
|
system.cpu.num_int_insts 374297244 # number of integer instructions
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.num_fp_insts 0 # number of float instructions
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.num_int_register_reads 801267455 # number of times the integer registers were read
|
|
|
|
|
system.cpu.num_int_register_writes 401624559 # number of times the integer registers were written
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
|
|
|
|
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.num_mem_refs 35626519 # number of memory refs
|
|
|
|
|
system.cpu.num_load_insts 27217784 # Number of load instructions
|
|
|
|
|
system.cpu.num_store_insts 8408735 # Number of store instructions
|
|
|
|
|
system.cpu.num_idle_cycles 9770605338.086651 # Number of idle cycles
|
|
|
|
|
system.cpu.num_busy_cycles 453481192.913350 # Number of busy cycles
|
|
|
|
|
system.cpu.not_idle_fraction 0.044354 # Percentage of non-idle cycles
|
|
|
|
|
system.cpu.idle_fraction 0.955646 # Percentage of idle cycles
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
|
|
|
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.icache.replacements 790795 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 510.627676 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 243365777 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 791307 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 307.549127 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.warmup_cycle 148763105500 # Cycle when the warmup percentage was hit.
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.icache.occ_blocks::cpu.inst 510.627676 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.icache.occ_percent::cpu.inst 0.997320 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.occ_percent::total 0.997320 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 243365777 # number of ReadReq hits
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.icache.ReadReq_hits::total 243365777 # number of ReadReq hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.icache.demand_hits::cpu.inst 243365777 # number of demand (read+write) hits
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.icache.demand_hits::total 243365777 # number of demand (read+write) hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.icache.overall_hits::cpu.inst 243365777 # number of overall hits
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.icache.overall_hits::total 243365777 # number of overall hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 791314 # number of ReadReq misses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.icache.ReadReq_misses::total 791314 # number of ReadReq misses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.icache.demand_misses::cpu.inst 791314 # number of demand (read+write) misses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.icache.demand_misses::total 791314 # number of demand (read+write) misses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.icache.overall_misses::cpu.inst 791314 # number of overall misses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.icache.overall_misses::total 791314 # number of overall misses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 244157091 # number of ReadReq accesses(hits+misses)
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.icache.ReadReq_accesses::total 244157091 # number of ReadReq accesses(hits+misses)
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.icache.demand_accesses::cpu.inst 244157091 # number of demand (read+write) accesses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.icache.demand_accesses::total 244157091 # number of demand (read+write) accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.icache.overall_accesses::cpu.inst 244157091 # number of overall (read+write) accesses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.icache.overall_accesses::total 244157091 # number of overall (read+write) accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003241 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.003241 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.003241 # miss rate for overall accesses
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.icache.writebacks::writebacks 809 # number of writebacks
|
|
|
|
|
system.cpu.icache.writebacks::total 809 # number of writebacks
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.itb_walker_cache.replacements 3435 # number of replacements
|
|
|
|
|
system.cpu.itb_walker_cache.tagsinuse 3.021701 # Cycle average of tags in use
|
|
|
|
|
system.cpu.itb_walker_cache.total_refs 7940 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.itb_walker_cache.sampled_refs 3444 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.itb_walker_cache.avg_refs 2.305459 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.itb_walker_cache.warmup_cycle 5105275407500 # Cycle when the warmup percentage was hit.
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.021701 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.188856 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.itb_walker_cache.occ_percent::total 0.188856 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7947 # number of ReadReq hits
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.itb_walker_cache.ReadReq_hits::total 7947 # number of ReadReq hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7949 # number of demand (read+write) hits
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.itb_walker_cache.demand_hits::total 7949 # number of demand (read+write) hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7949 # number of overall hits
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.itb_walker_cache.overall_hits::total 7949 # number of overall hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4278 # number of ReadReq misses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.itb_walker_cache.ReadReq_misses::total 4278 # number of ReadReq misses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4278 # number of demand (read+write) misses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.itb_walker_cache.demand_misses::total 4278 # number of demand (read+write) misses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4278 # number of overall misses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.itb_walker_cache.overall_misses::total 4278 # number of overall misses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12225 # number of ReadReq accesses(hits+misses)
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.itb_walker_cache.ReadReq_accesses::total 12225 # number of ReadReq accesses(hits+misses)
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12227 # number of demand (read+write) accesses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.itb_walker_cache.demand_accesses::total 12227 # number of demand (read+write) accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12227 # number of overall (read+write) accesses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.349939 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.349881 # miss rate for demand accesses
|
|
|
|
|
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.349881 # miss rate for overall accesses
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.itb_walker_cache.writebacks::writebacks 518 # number of writebacks
|
|
|
|
|
system.cpu.itb_walker_cache.writebacks::total 518 # number of writebacks
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.dtb_walker_cache.replacements 7755 # number of replacements
|
|
|
|
|
system.cpu.dtb_walker_cache.tagsinuse 5.010998 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dtb_walker_cache.total_refs 12854 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dtb_walker_cache.sampled_refs 7767 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dtb_walker_cache.avg_refs 1.654950 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dtb_walker_cache.warmup_cycle 5101232849000 # Cycle when the warmup percentage was hit.
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.010998 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313187 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dtb_walker_cache.occ_percent::total 0.313187 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12875 # number of ReadReq hits
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.dtb_walker_cache.ReadReq_hits::total 12875 # number of ReadReq hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12875 # number of demand (read+write) hits
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.dtb_walker_cache.demand_hits::total 12875 # number of demand (read+write) hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12875 # number of overall hits
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.dtb_walker_cache.overall_hits::total 12875 # number of overall hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8933 # number of ReadReq misses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.dtb_walker_cache.ReadReq_misses::total 8933 # number of ReadReq misses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8933 # number of demand (read+write) misses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.dtb_walker_cache.demand_misses::total 8933 # number of demand (read+write) misses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8933 # number of overall misses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.dtb_walker_cache.overall_misses::total 8933 # number of overall misses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21808 # number of ReadReq accesses(hits+misses)
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.dtb_walker_cache.ReadReq_accesses::total 21808 # number of ReadReq accesses(hits+misses)
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21808 # number of demand (read+write) accesses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.dtb_walker_cache.demand_accesses::total 21808 # number of demand (read+write) accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21808 # number of overall (read+write) accesses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.dtb_walker_cache.overall_accesses::total 21808 # number of overall (read+write) accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.409620 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.409620 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.409620 # miss rate for overall accesses
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dtb_walker_cache.writebacks::writebacks 2517 # number of writebacks
|
|
|
|
|
system.cpu.dtb_walker_cache.writebacks::total 2517 # number of writebacks
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.dcache.replacements 1621277 # number of replacements
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.dcache.tagsinuse 511.999417 # Cycle average of tags in use
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.dcache.total_refs 20142220 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 1621789 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 12.419754 # Average number of references to valid blocks.
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.occ_blocks::cpu.data 511.999417 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.dcache.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.occ_percent::total 0.999999 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 12057024 # number of ReadReq hits
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.dcache.ReadReq_hits::total 12057024 # number of ReadReq hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 8082938 # number of WriteReq hits
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.dcache.WriteReq_hits::total 8082938 # number of WriteReq hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.demand_hits::cpu.data 20139962 # number of demand (read+write) hits
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.dcache.demand_hits::total 20139962 # number of demand (read+write) hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.overall_hits::cpu.data 20139962 # number of overall hits
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.dcache.overall_hits::total 20139962 # number of overall hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1308207 # number of ReadReq misses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.dcache.ReadReq_misses::total 1308207 # number of ReadReq misses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 315850 # number of WriteReq misses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.dcache.WriteReq_misses::total 315850 # number of WriteReq misses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.demand_misses::cpu.data 1624057 # number of demand (read+write) misses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.dcache.demand_misses::total 1624057 # number of demand (read+write) misses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.overall_misses::cpu.data 1624057 # number of overall misses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.dcache.overall_misses::total 1624057 # number of overall misses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 13365231 # number of ReadReq accesses(hits+misses)
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.dcache.ReadReq_accesses::total 13365231 # number of ReadReq accesses(hits+misses)
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 8398788 # number of WriteReq accesses(hits+misses)
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.dcache.WriteReq_accesses::total 8398788 # number of WriteReq accesses(hits+misses)
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.demand_accesses::cpu.data 21764019 # number of demand (read+write) accesses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.dcache.demand_accesses::total 21764019 # number of demand (read+write) accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.overall_accesses::cpu.data 21764019 # number of overall (read+write) accesses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.dcache.overall_accesses::total 21764019 # number of overall (read+write) accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097881 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037607 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.074621 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.074621 # miss rate for overall accesses
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.writebacks::writebacks 1525559 # number of writebacks
|
|
|
|
|
system.cpu.dcache.writebacks::total 1525559 # number of writebacks
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-02-07 10:23:16 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
