2006-04-23 00:26:48 +02:00
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/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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2006-06-07 22:02:55 +02:00
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*
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* Authors: Kevin Lim
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* Korey Sewell
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2006-04-23 00:26:48 +02:00
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*/
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2006-10-23 20:00:07 +02:00
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#include "arch/locked_mem.hh"
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2006-06-16 23:08:47 +02:00
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#include "config/use_checker.hh"
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2006-07-13 19:12:51 +02:00
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#include "cpu/o3/lsq.hh"
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2006-04-23 00:26:48 +02:00
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#include "cpu/o3/lsq_unit.hh"
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#include "base/str.hh"
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2006-06-13 17:38:16 +02:00
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#include "mem/packet.hh"
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2006-06-03 00:15:20 +02:00
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#include "mem/request.hh"
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2006-04-23 00:26:48 +02:00
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2006-06-23 00:09:31 +02:00
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#if USE_CHECKER
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#include "cpu/checker/cpu.hh"
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#endif
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2006-06-03 00:15:20 +02:00
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template<class Impl>
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2006-06-06 00:14:39 +02:00
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LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
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LSQUnit *lsq_ptr)
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2008-10-09 13:58:24 +02:00
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: inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
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2006-06-03 00:15:20 +02:00
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{
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2006-06-06 00:14:39 +02:00
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this->setFlags(Event::AutoDelete);
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}
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2006-06-03 00:15:20 +02:00
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2006-06-06 00:14:39 +02:00
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template<class Impl>
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void
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LSQUnit<Impl>::WritebackEvent::process()
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{
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if (!lsqPtr->isSwitchedOut()) {
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lsqPtr->writeback(inst, pkt);
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2006-06-03 00:15:20 +02:00
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}
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2007-04-03 20:25:24 +02:00
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if (pkt->senderState)
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delete pkt->senderState;
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delete pkt->req;
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2006-06-06 00:14:39 +02:00
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delete pkt;
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}
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2006-06-03 00:15:20 +02:00
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2006-06-06 00:14:39 +02:00
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template<class Impl>
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const char *
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2008-02-06 22:32:40 +01:00
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LSQUnit<Impl>::WritebackEvent::description() const
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2006-06-06 00:14:39 +02:00
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{
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2007-07-01 02:45:58 +02:00
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return "Store writeback";
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2006-04-23 00:26:48 +02:00
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}
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2006-06-03 00:15:20 +02:00
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template<class Impl>
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2006-04-23 00:26:48 +02:00
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void
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2006-06-06 00:14:39 +02:00
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LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
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2006-04-23 00:26:48 +02:00
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{
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2006-06-06 00:14:39 +02:00
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LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
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DynInstPtr inst = state->inst;
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DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum);
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2006-06-09 22:28:17 +02:00
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DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum);
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2006-04-23 00:26:48 +02:00
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2006-06-06 00:14:39 +02:00
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//iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
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2006-05-25 20:41:36 +02:00
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2007-08-27 06:45:40 +02:00
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assert(!pkt->wasNacked());
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2006-06-06 00:14:39 +02:00
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if (isSwitchedOut() || inst->isSquashed()) {
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2006-07-05 21:51:36 +02:00
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iewStage->decrWb(inst->seqNum);
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2006-06-06 00:14:39 +02:00
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} else {
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if (!state->noWB) {
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writeback(inst, pkt);
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}
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2006-05-04 17:36:20 +02:00
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2006-06-06 00:14:39 +02:00
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if (inst->isStore()) {
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completeStore(state->idx);
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}
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}
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2006-06-03 00:15:20 +02:00
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2006-06-06 00:14:39 +02:00
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delete state;
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2007-03-23 16:33:08 +01:00
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delete pkt->req;
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2006-06-06 00:14:39 +02:00
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delete pkt;
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2006-06-03 00:15:20 +02:00
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}
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2006-04-23 00:26:48 +02:00
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template <class Impl>
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LSQUnit<Impl>::LSQUnit()
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2006-06-06 00:14:39 +02:00
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: loads(0), stores(0), storesToWB(0), stalled(false),
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isStoreBlocked(false), isLoadBlocked(false),
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2006-04-23 00:26:48 +02:00
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loadBlockedHandled(false)
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{
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}
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template<class Impl>
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void
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2008-08-11 21:22:16 +02:00
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LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params,
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LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries,
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unsigned id)
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2006-04-23 00:26:48 +02:00
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{
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2007-04-04 21:38:59 +02:00
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cpu = cpu_ptr;
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iewStage = iew_ptr;
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DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id);
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2006-04-23 00:26:48 +02:00
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2006-05-04 17:36:20 +02:00
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switchedOut = false;
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2006-07-13 19:12:51 +02:00
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lsq = lsq_ptr;
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2006-04-23 00:26:48 +02:00
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lsqID = id;
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2006-05-19 21:53:17 +02:00
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// Add 1 for the sentinel entry (they are circular queues).
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LQEntries = maxLQEntries + 1;
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SQEntries = maxSQEntries + 1;
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2006-04-23 00:26:48 +02:00
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loadQueue.resize(LQEntries);
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storeQueue.resize(SQEntries);
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loadHead = loadTail = 0;
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storeHead = storeWBIdx = storeTail = 0;
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usedPorts = 0;
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cachePorts = params->cachePorts;
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2006-11-06 02:29:38 +01:00
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retryPkt = NULL;
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2006-05-19 21:53:17 +02:00
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memDepViolator = NULL;
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2006-04-23 00:26:48 +02:00
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blockedLoadSeqNum = 0;
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}
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template<class Impl>
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std::string
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LSQUnit<Impl>::name() const
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{
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if (Impl::MaxThreads == 1) {
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return iewStage->name() + ".lsq";
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} else {
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return iewStage->name() + ".lsq.thread." + to_string(lsqID);
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}
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}
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2006-06-14 04:35:05 +02:00
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template<class Impl>
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void
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LSQUnit<Impl>::regStats()
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{
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lsqForwLoads
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.name(name() + ".forwLoads")
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.desc("Number of loads that had data forwarded from stores");
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invAddrLoads
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.name(name() + ".invAddrLoads")
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.desc("Number of loads ignored due to an invalid address");
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lsqSquashedLoads
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.name(name() + ".squashedLoads")
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.desc("Number of loads squashed");
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lsqIgnoredResponses
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.name(name() + ".ignoredResponses")
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.desc("Number of memory responses ignored because the instruction is squashed");
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2006-08-24 23:29:34 +02:00
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lsqMemOrderViolation
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.name(name() + ".memOrderViolation")
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.desc("Number of memory ordering violations");
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2006-06-14 04:35:05 +02:00
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lsqSquashedStores
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.name(name() + ".squashedStores")
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.desc("Number of stores squashed");
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invAddrSwpfs
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.name(name() + ".invAddrSwpfs")
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.desc("Number of software prefetches ignored due to an invalid address");
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lsqBlockedLoads
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.name(name() + ".blockedLoads")
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.desc("Number of blocked loads due to partial load-store forwarding");
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lsqRescheduledLoads
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.name(name() + ".rescheduledLoads")
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.desc("Number of loads that were rescheduled");
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lsqCacheBlocked
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.name(name() + ".cacheBlocked")
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.desc("Number of times an access to memory failed due to the cache being blocked");
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}
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2007-04-04 21:38:59 +02:00
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template<class Impl>
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void
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LSQUnit<Impl>::setDcachePort(Port *dcache_port)
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{
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dcachePort = dcache_port;
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#if USE_CHECKER
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if (cpu->checker) {
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cpu->checker->setDcachePort(dcachePort);
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}
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#endif
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}
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2006-04-23 00:26:48 +02:00
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template<class Impl>
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void
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LSQUnit<Impl>::clearLQ()
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{
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loadQueue.clear();
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}
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template<class Impl>
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void
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LSQUnit<Impl>::clearSQ()
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{
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storeQueue.clear();
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}
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2006-05-04 17:36:20 +02:00
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template<class Impl>
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void
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LSQUnit<Impl>::switchOut()
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{
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switchedOut = true;
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2006-09-28 06:09:27 +02:00
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for (int i = 0; i < loadQueue.size(); ++i) {
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assert(!loadQueue[i]);
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2006-05-04 17:36:20 +02:00
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loadQueue[i] = NULL;
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2006-09-28 06:09:27 +02:00
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}
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2006-05-04 17:36:20 +02:00
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2006-05-19 21:53:17 +02:00
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assert(storesToWB == 0);
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2006-05-04 17:36:20 +02:00
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}
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template<class Impl>
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void
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LSQUnit<Impl>::takeOverFrom()
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{
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switchedOut = false;
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loads = stores = storesToWB = 0;
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loadHead = loadTail = 0;
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storeHead = storeWBIdx = storeTail = 0;
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usedPorts = 0;
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2006-05-19 21:53:17 +02:00
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memDepViolator = NULL;
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2006-05-04 17:36:20 +02:00
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blockedLoadSeqNum = 0;
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stalled = false;
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isLoadBlocked = false;
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loadBlockedHandled = false;
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}
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2006-04-23 00:26:48 +02:00
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template<class Impl>
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void
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LSQUnit<Impl>::resizeLQ(unsigned size)
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{
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2006-05-19 21:53:17 +02:00
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unsigned size_plus_sentinel = size + 1;
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assert(size_plus_sentinel >= LQEntries);
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2006-04-23 00:26:48 +02:00
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2006-05-19 21:53:17 +02:00
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if (size_plus_sentinel > LQEntries) {
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while (size_plus_sentinel > loadQueue.size()) {
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2006-04-23 00:26:48 +02:00
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DynInstPtr dummy;
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loadQueue.push_back(dummy);
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LQEntries++;
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}
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} else {
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2006-05-19 21:53:17 +02:00
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LQEntries = size_plus_sentinel;
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2006-04-23 00:26:48 +02:00
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}
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}
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template<class Impl>
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void
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LSQUnit<Impl>::resizeSQ(unsigned size)
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{
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2006-05-19 21:53:17 +02:00
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unsigned size_plus_sentinel = size + 1;
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if (size_plus_sentinel > SQEntries) {
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while (size_plus_sentinel > storeQueue.size()) {
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2006-04-23 00:26:48 +02:00
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SQEntry dummy;
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storeQueue.push_back(dummy);
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SQEntries++;
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}
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} else {
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2006-05-19 21:53:17 +02:00
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SQEntries = size_plus_sentinel;
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2006-04-23 00:26:48 +02:00
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}
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}
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template <class Impl>
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void
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LSQUnit<Impl>::insert(DynInstPtr &inst)
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{
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assert(inst->isMemRef());
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assert(inst->isLoad() || inst->isStore());
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if (inst->isLoad()) {
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insertLoad(inst);
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} else {
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insertStore(inst);
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}
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inst->setInLSQ();
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}
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template <class Impl>
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void
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LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst)
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{
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2006-05-19 21:53:17 +02:00
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assert((loadTail + 1) % LQEntries != loadHead);
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assert(loads < LQEntries);
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2006-04-23 00:26:48 +02:00
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DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n",
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load_inst->readPC(), loadTail, load_inst->seqNum);
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load_inst->lqIdx = loadTail;
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if (stores == 0) {
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load_inst->sqIdx = -1;
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} else {
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load_inst->sqIdx = storeTail;
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|
}
|
|
|
|
|
|
|
|
loadQueue[loadTail] = load_inst;
|
|
|
|
|
|
|
|
incrLdIdx(loadTail);
|
|
|
|
|
|
|
|
++loads;
|
|
|
|
}
|
|
|
|
|
|
|
|
template <class Impl>
|
|
|
|
void
|
|
|
|
LSQUnit<Impl>::insertStore(DynInstPtr &store_inst)
|
|
|
|
{
|
|
|
|
// Make sure it is not full before inserting an instruction.
|
|
|
|
assert((storeTail + 1) % SQEntries != storeHead);
|
|
|
|
assert(stores < SQEntries);
|
|
|
|
|
|
|
|
DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n",
|
|
|
|
store_inst->readPC(), storeTail, store_inst->seqNum);
|
|
|
|
|
|
|
|
store_inst->sqIdx = storeTail;
|
|
|
|
store_inst->lqIdx = loadTail;
|
|
|
|
|
|
|
|
storeQueue[storeTail] = SQEntry(store_inst);
|
|
|
|
|
|
|
|
incrStIdx(storeTail);
|
|
|
|
|
|
|
|
++stores;
|
|
|
|
}
|
|
|
|
|
|
|
|
template <class Impl>
|
|
|
|
typename Impl::DynInstPtr
|
|
|
|
LSQUnit<Impl>::getMemDepViolator()
|
|
|
|
{
|
|
|
|
DynInstPtr temp = memDepViolator;
|
|
|
|
|
|
|
|
memDepViolator = NULL;
|
|
|
|
|
|
|
|
return temp;
|
|
|
|
}
|
|
|
|
|
|
|
|
template <class Impl>
|
|
|
|
unsigned
|
|
|
|
LSQUnit<Impl>::numFreeEntries()
|
|
|
|
{
|
|
|
|
unsigned free_lq_entries = LQEntries - loads;
|
|
|
|
unsigned free_sq_entries = SQEntries - stores;
|
|
|
|
|
|
|
|
// Both the LQ and SQ entries have an extra dummy entry to differentiate
|
|
|
|
// empty/full conditions. Subtract 1 from the free entries.
|
|
|
|
if (free_lq_entries < free_sq_entries) {
|
|
|
|
return free_lq_entries - 1;
|
|
|
|
} else {
|
|
|
|
return free_sq_entries - 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
template <class Impl>
|
|
|
|
int
|
|
|
|
LSQUnit<Impl>::numLoadsReady()
|
|
|
|
{
|
|
|
|
int load_idx = loadHead;
|
|
|
|
int retval = 0;
|
|
|
|
|
|
|
|
while (load_idx != loadTail) {
|
|
|
|
assert(loadQueue[load_idx]);
|
|
|
|
|
|
|
|
if (loadQueue[load_idx]->readyToIssue()) {
|
|
|
|
++retval;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return retval;
|
|
|
|
}
|
|
|
|
|
|
|
|
template <class Impl>
|
|
|
|
Fault
|
|
|
|
LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
|
|
|
|
{
|
2007-03-23 16:33:08 +01:00
|
|
|
using namespace TheISA;
|
2006-04-23 00:26:48 +02:00
|
|
|
// Execute a specific load.
|
|
|
|
Fault load_fault = NoFault;
|
|
|
|
|
|
|
|
DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n",
|
|
|
|
inst->readPC(),inst->seqNum);
|
|
|
|
|
2007-03-23 16:33:08 +01:00
|
|
|
assert(!inst->isSquashed());
|
|
|
|
|
2006-06-03 00:15:20 +02:00
|
|
|
load_fault = inst->initiateAcc();
|
2006-04-23 00:26:48 +02:00
|
|
|
|
|
|
|
// If the instruction faulted, then we need to send it along to commit
|
|
|
|
// without the instruction completing.
|
|
|
|
if (load_fault != NoFault) {
|
2006-05-19 21:53:17 +02:00
|
|
|
// Send this instruction to commit, also make sure iew stage
|
|
|
|
// realizes there is activity.
|
2006-09-28 06:09:27 +02:00
|
|
|
// Mark it as executed unless it is an uncached load that
|
|
|
|
// needs to hit the head of commit.
|
2007-03-23 16:33:08 +01:00
|
|
|
if (!(inst->hasRequest() && inst->uncacheable()) ||
|
2006-12-12 05:51:21 +01:00
|
|
|
inst->isAtCommit()) {
|
2006-09-28 06:09:27 +02:00
|
|
|
inst->setExecuted();
|
|
|
|
}
|
2006-04-23 00:26:48 +02:00
|
|
|
iewStage->instToCommit(inst);
|
|
|
|
iewStage->activityThisCycle();
|
2007-03-23 16:33:08 +01:00
|
|
|
} else if (!loadBlocked()) {
|
|
|
|
assert(inst->effAddrValid);
|
|
|
|
int load_idx = inst->lqIdx;
|
|
|
|
incrLdIdx(load_idx);
|
|
|
|
while (load_idx != loadTail) {
|
|
|
|
// Really only need to check loads that have actually executed
|
|
|
|
|
|
|
|
// @todo: For now this is extra conservative, detecting a
|
|
|
|
// violation if the addresses match assuming all accesses
|
|
|
|
// are quad word accesses.
|
|
|
|
|
|
|
|
// @todo: Fix this, magic number being used here
|
|
|
|
if (loadQueue[load_idx]->effAddrValid &&
|
|
|
|
(loadQueue[load_idx]->effAddr >> 8) ==
|
|
|
|
(inst->effAddr >> 8)) {
|
|
|
|
// A load incorrectly passed this load. Squash and refetch.
|
|
|
|
// For now return a fault to show that it was unsuccessful.
|
|
|
|
DynInstPtr violator = loadQueue[load_idx];
|
|
|
|
if (!memDepViolator ||
|
|
|
|
(violator->seqNum < memDepViolator->seqNum)) {
|
|
|
|
memDepViolator = violator;
|
|
|
|
} else {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
++lsqMemOrderViolation;
|
|
|
|
|
|
|
|
return genMachineCheckFault();
|
|
|
|
}
|
|
|
|
|
|
|
|
incrLdIdx(load_idx);
|
|
|
|
}
|
2006-04-23 00:26:48 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
return load_fault;
|
|
|
|
}
|
|
|
|
|
|
|
|
template <class Impl>
|
|
|
|
Fault
|
|
|
|
LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)
|
|
|
|
{
|
|
|
|
using namespace TheISA;
|
|
|
|
// Make sure that a store exists.
|
|
|
|
assert(stores != 0);
|
|
|
|
|
|
|
|
int store_idx = store_inst->sqIdx;
|
|
|
|
|
|
|
|
DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n",
|
|
|
|
store_inst->readPC(), store_inst->seqNum);
|
|
|
|
|
2007-03-23 16:33:08 +01:00
|
|
|
assert(!store_inst->isSquashed());
|
|
|
|
|
2006-04-23 00:26:48 +02:00
|
|
|
// Check the recently completed loads to see if any match this store's
|
|
|
|
// address. If so, then we have a memory ordering violation.
|
|
|
|
int load_idx = store_inst->lqIdx;
|
|
|
|
|
|
|
|
Fault store_fault = store_inst->initiateAcc();
|
|
|
|
|
2006-05-19 21:53:17 +02:00
|
|
|
if (storeQueue[store_idx].size == 0) {
|
2006-04-23 00:26:48 +02:00
|
|
|
DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n",
|
|
|
|
store_inst->readPC(),store_inst->seqNum);
|
|
|
|
|
|
|
|
return store_fault;
|
|
|
|
}
|
|
|
|
|
|
|
|
assert(store_fault == NoFault);
|
|
|
|
|
2006-05-23 20:38:16 +02:00
|
|
|
if (store_inst->isStoreConditional()) {
|
|
|
|
// Store conditionals need to set themselves as able to
|
|
|
|
// writeback if we haven't had a fault by here.
|
2006-05-19 21:53:17 +02:00
|
|
|
storeQueue[store_idx].canWB = true;
|
2006-04-23 00:26:48 +02:00
|
|
|
|
2006-05-19 21:53:17 +02:00
|
|
|
++storesToWB;
|
2006-04-23 00:26:48 +02:00
|
|
|
}
|
|
|
|
|
2007-03-23 16:33:08 +01:00
|
|
|
assert(store_inst->effAddrValid);
|
|
|
|
while (load_idx != loadTail) {
|
|
|
|
// Really only need to check loads that have actually executed
|
|
|
|
// It's safe to check all loads because effAddr is set to
|
|
|
|
// InvalAddr when the dyn inst is created.
|
|
|
|
|
|
|
|
// @todo: For now this is extra conservative, detecting a
|
|
|
|
// violation if the addresses match assuming all accesses
|
|
|
|
// are quad word accesses.
|
|
|
|
|
|
|
|
// @todo: Fix this, magic number being used here
|
|
|
|
if (loadQueue[load_idx]->effAddrValid &&
|
|
|
|
(loadQueue[load_idx]->effAddr >> 8) ==
|
|
|
|
(store_inst->effAddr >> 8)) {
|
|
|
|
// A load incorrectly passed this store. Squash and refetch.
|
|
|
|
// For now return a fault to show that it was unsuccessful.
|
|
|
|
DynInstPtr violator = loadQueue[load_idx];
|
|
|
|
if (!memDepViolator ||
|
|
|
|
(violator->seqNum < memDepViolator->seqNum)) {
|
|
|
|
memDepViolator = violator;
|
|
|
|
} else {
|
|
|
|
break;
|
2006-04-23 00:26:48 +02:00
|
|
|
}
|
|
|
|
|
2007-03-23 16:33:08 +01:00
|
|
|
++lsqMemOrderViolation;
|
|
|
|
|
|
|
|
return genMachineCheckFault();
|
2006-04-23 00:26:48 +02:00
|
|
|
}
|
|
|
|
|
2007-03-23 16:33:08 +01:00
|
|
|
incrLdIdx(load_idx);
|
2006-04-23 00:26:48 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
return store_fault;
|
|
|
|
}
|
|
|
|
|
|
|
|
template <class Impl>
|
|
|
|
void
|
|
|
|
LSQUnit<Impl>::commitLoad()
|
|
|
|
{
|
|
|
|
assert(loadQueue[loadHead]);
|
|
|
|
|
|
|
|
DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n",
|
|
|
|
loadQueue[loadHead]->readPC());
|
|
|
|
|
|
|
|
loadQueue[loadHead] = NULL;
|
|
|
|
|
|
|
|
incrLdIdx(loadHead);
|
|
|
|
|
|
|
|
--loads;
|
|
|
|
}
|
|
|
|
|
|
|
|
template <class Impl>
|
|
|
|
void
|
|
|
|
LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst)
|
|
|
|
{
|
|
|
|
assert(loads == 0 || loadQueue[loadHead]);
|
|
|
|
|
|
|
|
while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) {
|
|
|
|
commitLoad();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
template <class Impl>
|
|
|
|
void
|
|
|
|
LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst)
|
|
|
|
{
|
|
|
|
assert(stores == 0 || storeQueue[storeHead].inst);
|
|
|
|
|
|
|
|
int store_idx = storeHead;
|
|
|
|
|
|
|
|
while (store_idx != storeTail) {
|
|
|
|
assert(storeQueue[store_idx].inst);
|
2006-05-19 21:53:17 +02:00
|
|
|
// Mark any stores that are now committed and have not yet
|
|
|
|
// been marked as able to write back.
|
2006-04-23 00:26:48 +02:00
|
|
|
if (!storeQueue[store_idx].canWB) {
|
|
|
|
if (storeQueue[store_idx].inst->seqNum > youngest_inst) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
DPRINTF(LSQUnit, "Marking store as able to write back, PC "
|
|
|
|
"%#x [sn:%lli]\n",
|
|
|
|
storeQueue[store_idx].inst->readPC(),
|
|
|
|
storeQueue[store_idx].inst->seqNum);
|
|
|
|
|
|
|
|
storeQueue[store_idx].canWB = true;
|
|
|
|
|
|
|
|
++storesToWB;
|
|
|
|
}
|
|
|
|
|
|
|
|
incrStIdx(store_idx);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
template <class Impl>
|
|
|
|
void
|
|
|
|
LSQUnit<Impl>::writebackStores()
|
|
|
|
{
|
|
|
|
while (storesToWB > 0 &&
|
|
|
|
storeWBIdx != storeTail &&
|
|
|
|
storeQueue[storeWBIdx].inst &&
|
|
|
|
storeQueue[storeWBIdx].canWB &&
|
|
|
|
usedPorts < cachePorts) {
|
|
|
|
|
2006-07-13 19:12:51 +02:00
|
|
|
if (isStoreBlocked || lsq->cacheBlocked()) {
|
2006-06-06 00:14:39 +02:00
|
|
|
DPRINTF(LSQUnit, "Unable to write back any more stores, cache"
|
|
|
|
" is blocked!\n");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2006-05-19 21:53:17 +02:00
|
|
|
// Store didn't write any data so no need to write it back to
|
|
|
|
// memory.
|
2006-04-23 00:26:48 +02:00
|
|
|
if (storeQueue[storeWBIdx].size == 0) {
|
|
|
|
completeStore(storeWBIdx);
|
|
|
|
|
|
|
|
incrStIdx(storeWBIdx);
|
|
|
|
|
|
|
|
continue;
|
|
|
|
}
|
2006-06-06 00:14:39 +02:00
|
|
|
|
2006-04-23 00:26:48 +02:00
|
|
|
++usedPorts;
|
|
|
|
|
|
|
|
if (storeQueue[storeWBIdx].inst->isDataPrefetch()) {
|
|
|
|
incrStIdx(storeWBIdx);
|
|
|
|
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
assert(storeQueue[storeWBIdx].req);
|
|
|
|
assert(!storeQueue[storeWBIdx].committed);
|
|
|
|
|
2006-06-03 00:15:20 +02:00
|
|
|
DynInstPtr inst = storeQueue[storeWBIdx].inst;
|
|
|
|
|
|
|
|
Request *req = storeQueue[storeWBIdx].req;
|
2006-04-23 00:26:48 +02:00
|
|
|
storeQueue[storeWBIdx].committed = true;
|
|
|
|
|
2006-06-03 00:15:20 +02:00
|
|
|
assert(!inst->memData);
|
|
|
|
inst->memData = new uint8_t[64];
|
2006-12-06 11:54:16 +01:00
|
|
|
|
2007-04-04 00:53:26 +02:00
|
|
|
memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize());
|
2006-06-03 00:15:20 +02:00
|
|
|
|
2007-07-01 05:35:42 +02:00
|
|
|
MemCmd command =
|
|
|
|
req->isSwap() ? MemCmd::SwapReq :
|
2009-04-19 13:25:01 +02:00
|
|
|
(req->isLlsc() ? MemCmd::StoreCondReq : MemCmd::WriteReq);
|
2007-04-08 03:42:42 +02:00
|
|
|
PacketPtr data_pkt = new Packet(req, command,
|
2007-02-07 19:53:37 +01:00
|
|
|
Packet::Broadcast);
|
2006-06-03 00:15:20 +02:00
|
|
|
data_pkt->dataStatic(inst->memData);
|
2006-04-23 00:26:48 +02:00
|
|
|
|
2006-06-06 00:14:39 +02:00
|
|
|
LSQSenderState *state = new LSQSenderState;
|
|
|
|
state->isLoad = false;
|
|
|
|
state->idx = storeWBIdx;
|
|
|
|
state->inst = inst;
|
|
|
|
data_pkt->senderState = state;
|
|
|
|
|
2006-04-23 00:26:48 +02:00
|
|
|
DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
|
|
|
|
"to Addr:%#x, data:%#x [sn:%lli]\n",
|
2006-10-08 06:53:41 +02:00
|
|
|
storeWBIdx, inst->readPC(),
|
2006-12-16 13:34:34 +01:00
|
|
|
req->getPaddr(), (int)*(inst->memData),
|
2006-10-08 06:53:41 +02:00
|
|
|
inst->seqNum);
|
2006-04-23 00:26:48 +02:00
|
|
|
|
2006-06-09 17:46:35 +02:00
|
|
|
// @todo: Remove this SC hack once the memory system handles it.
|
2007-04-08 03:42:42 +02:00
|
|
|
if (inst->isStoreConditional()) {
|
2006-10-23 20:00:07 +02:00
|
|
|
// Disable recording the result temporarily. Writing to
|
|
|
|
// misc regs normally updates the result, but this is not
|
|
|
|
// the desired behavior when handling store conditionals.
|
|
|
|
inst->recordResult = false;
|
|
|
|
bool success = TheISA::handleLockedWrite(inst.get(), req);
|
|
|
|
inst->recordResult = true;
|
|
|
|
|
|
|
|
if (!success) {
|
|
|
|
// Instantly complete this store.
|
|
|
|
DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. "
|
|
|
|
"Instantly completing it.\n",
|
|
|
|
inst->seqNum);
|
|
|
|
WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
|
2008-10-09 13:58:24 +02:00
|
|
|
cpu->schedule(wb, curTick + 1);
|
2006-10-23 20:00:07 +02:00
|
|
|
completeStore(storeWBIdx);
|
|
|
|
incrStIdx(storeWBIdx);
|
|
|
|
continue;
|
2006-05-19 21:53:17 +02:00
|
|
|
}
|
2006-06-09 17:46:35 +02:00
|
|
|
} else {
|
|
|
|
// Non-store conditionals do not need a writeback.
|
|
|
|
state->noWB = true;
|
|
|
|
}
|
2006-06-06 00:14:39 +02:00
|
|
|
|
2006-06-09 17:46:35 +02:00
|
|
|
if (!dcachePort->sendTiming(data_pkt)) {
|
|
|
|
// Need to handle becoming blocked on a store.
|
2007-03-23 16:33:08 +01:00
|
|
|
DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will"
|
2006-10-08 06:53:41 +02:00
|
|
|
"retry later\n",
|
|
|
|
inst->seqNum);
|
2006-06-09 17:46:35 +02:00
|
|
|
isStoreBlocked = true;
|
2006-06-14 04:35:05 +02:00
|
|
|
++lsqCacheBlocked;
|
2006-06-09 22:28:17 +02:00
|
|
|
assert(retryPkt == NULL);
|
|
|
|
retryPkt = data_pkt;
|
2006-08-16 21:56:22 +02:00
|
|
|
lsq->setRetryTid(lsqID);
|
2006-06-09 17:46:35 +02:00
|
|
|
} else {
|
|
|
|
storePostSend(data_pkt);
|
2006-04-23 00:26:48 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Not sure this should set it to 0.
|
|
|
|
usedPorts = 0;
|
|
|
|
|
|
|
|
assert(stores >= 0 && storesToWB >= 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*template <class Impl>
|
|
|
|
void
|
|
|
|
LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum)
|
|
|
|
{
|
|
|
|
list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(),
|
|
|
|
mshrSeqNums.end(),
|
|
|
|
seqNum);
|
|
|
|
|
|
|
|
if (mshr_it != mshrSeqNums.end()) {
|
|
|
|
mshrSeqNums.erase(mshr_it);
|
|
|
|
DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size());
|
|
|
|
}
|
|
|
|
}*/
|
|
|
|
|
|
|
|
template <class Impl>
|
|
|
|
void
|
|
|
|
LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
|
|
|
|
{
|
|
|
|
DPRINTF(LSQUnit, "Squashing until [sn:%lli]!"
|
2006-05-19 21:53:17 +02:00
|
|
|
"(Loads:%i Stores:%i)\n", squashed_num, loads, stores);
|
2006-04-23 00:26:48 +02:00
|
|
|
|
|
|
|
int load_idx = loadTail;
|
|
|
|
decrLdIdx(load_idx);
|
|
|
|
|
|
|
|
while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) {
|
|
|
|
DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, "
|
|
|
|
"[sn:%lli]\n",
|
|
|
|
loadQueue[load_idx]->readPC(),
|
|
|
|
loadQueue[load_idx]->seqNum);
|
|
|
|
|
|
|
|
if (isStalled() && load_idx == stallingLoadIdx) {
|
|
|
|
stalled = false;
|
|
|
|
stallingStoreIsn = 0;
|
|
|
|
stallingLoadIdx = 0;
|
|
|
|
}
|
|
|
|
|
2006-05-19 21:53:17 +02:00
|
|
|
// Clear the smart pointer to make sure it is decremented.
|
2006-06-14 19:12:41 +02:00
|
|
|
loadQueue[load_idx]->setSquashed();
|
2006-04-23 00:26:48 +02:00
|
|
|
loadQueue[load_idx] = NULL;
|
|
|
|
--loads;
|
|
|
|
|
|
|
|
// Inefficient!
|
|
|
|
loadTail = load_idx;
|
|
|
|
|
|
|
|
decrLdIdx(load_idx);
|
2006-06-14 04:35:05 +02:00
|
|
|
++lsqSquashedLoads;
|
2006-04-23 00:26:48 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
if (isLoadBlocked) {
|
|
|
|
if (squashed_num < blockedLoadSeqNum) {
|
|
|
|
isLoadBlocked = false;
|
|
|
|
loadBlockedHandled = false;
|
|
|
|
blockedLoadSeqNum = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-03-23 16:33:08 +01:00
|
|
|
if (memDepViolator && squashed_num < memDepViolator->seqNum) {
|
|
|
|
memDepViolator = NULL;
|
|
|
|
}
|
|
|
|
|
2006-04-23 00:26:48 +02:00
|
|
|
int store_idx = storeTail;
|
|
|
|
decrStIdx(store_idx);
|
|
|
|
|
|
|
|
while (stores != 0 &&
|
|
|
|
storeQueue[store_idx].inst->seqNum > squashed_num) {
|
2006-05-19 21:53:17 +02:00
|
|
|
// Instructions marked as can WB are already committed.
|
2006-04-23 00:26:48 +02:00
|
|
|
if (storeQueue[store_idx].canWB) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, "
|
|
|
|
"idx:%i [sn:%lli]\n",
|
|
|
|
storeQueue[store_idx].inst->readPC(),
|
|
|
|
store_idx, storeQueue[store_idx].inst->seqNum);
|
|
|
|
|
2006-05-19 21:53:17 +02:00
|
|
|
// I don't think this can happen. It should have been cleared
|
|
|
|
// by the stalling load.
|
2006-04-23 00:26:48 +02:00
|
|
|
if (isStalled() &&
|
|
|
|
storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
|
|
|
|
panic("Is stalled should have been cleared by stalling load!\n");
|
|
|
|
stalled = false;
|
|
|
|
stallingStoreIsn = 0;
|
|
|
|
}
|
|
|
|
|
2006-05-19 21:53:17 +02:00
|
|
|
// Clear the smart pointer to make sure it is decremented.
|
2006-06-14 19:12:41 +02:00
|
|
|
storeQueue[store_idx].inst->setSquashed();
|
2006-04-23 00:26:48 +02:00
|
|
|
storeQueue[store_idx].inst = NULL;
|
|
|
|
storeQueue[store_idx].canWB = 0;
|
|
|
|
|
2007-03-23 16:33:08 +01:00
|
|
|
// Must delete request now that it wasn't handed off to
|
|
|
|
// memory. This is quite ugly. @todo: Figure out the proper
|
|
|
|
// place to really handle request deletes.
|
|
|
|
delete storeQueue[store_idx].req;
|
|
|
|
|
2006-04-23 00:26:48 +02:00
|
|
|
storeQueue[store_idx].req = NULL;
|
|
|
|
--stores;
|
|
|
|
|
|
|
|
// Inefficient!
|
|
|
|
storeTail = store_idx;
|
|
|
|
|
|
|
|
decrStIdx(store_idx);
|
2006-06-14 04:35:05 +02:00
|
|
|
++lsqSquashedStores;
|
2006-04-23 00:26:48 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-06-09 17:46:35 +02:00
|
|
|
template <class Impl>
|
|
|
|
void
|
2006-10-20 09:10:12 +02:00
|
|
|
LSQUnit<Impl>::storePostSend(PacketPtr pkt)
|
2006-06-09 17:46:35 +02:00
|
|
|
{
|
|
|
|
if (isStalled() &&
|
|
|
|
storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) {
|
|
|
|
DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
|
|
|
|
"load idx:%i\n",
|
|
|
|
stallingStoreIsn, stallingLoadIdx);
|
|
|
|
stalled = false;
|
|
|
|
stallingStoreIsn = 0;
|
|
|
|
iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!storeQueue[storeWBIdx].inst->isStoreConditional()) {
|
|
|
|
// The store is basically completed at this time. This
|
|
|
|
// only works so long as the checker doesn't try to
|
|
|
|
// verify the value in memory for stores.
|
|
|
|
storeQueue[storeWBIdx].inst->setCompleted();
|
2006-06-16 23:08:47 +02:00
|
|
|
#if USE_CHECKER
|
2006-06-09 17:46:35 +02:00
|
|
|
if (cpu->checker) {
|
2006-06-16 19:10:47 +02:00
|
|
|
cpu->checker->verify(storeQueue[storeWBIdx].inst);
|
2006-06-09 17:46:35 +02:00
|
|
|
}
|
2006-06-16 23:08:47 +02:00
|
|
|
#endif
|
2006-06-09 17:46:35 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
incrStIdx(storeWBIdx);
|
|
|
|
}
|
|
|
|
|
2006-06-06 00:14:39 +02:00
|
|
|
template <class Impl>
|
|
|
|
void
|
|
|
|
LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt)
|
|
|
|
{
|
|
|
|
iewStage->wakeCPU();
|
|
|
|
|
|
|
|
// Squashed instructions do not need to complete their access.
|
|
|
|
if (inst->isSquashed()) {
|
2006-07-19 21:28:02 +02:00
|
|
|
iewStage->decrWb(inst->seqNum);
|
2006-06-06 00:14:39 +02:00
|
|
|
assert(!inst->isStore());
|
2006-06-14 04:35:05 +02:00
|
|
|
++lsqIgnoredResponses;
|
2006-06-06 00:14:39 +02:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!inst->isExecuted()) {
|
|
|
|
inst->setExecuted();
|
|
|
|
|
|
|
|
// Complete access to copy data to proper place.
|
|
|
|
inst->completeAcc(pkt);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Need to insert instruction into queue to commit
|
|
|
|
iewStage->instToCommit(inst);
|
|
|
|
|
|
|
|
iewStage->activityThisCycle();
|
|
|
|
}
|
|
|
|
|
2006-04-23 00:26:48 +02:00
|
|
|
template <class Impl>
|
|
|
|
void
|
|
|
|
LSQUnit<Impl>::completeStore(int store_idx)
|
|
|
|
{
|
|
|
|
assert(storeQueue[store_idx].inst);
|
|
|
|
storeQueue[store_idx].completed = true;
|
|
|
|
--storesToWB;
|
|
|
|
// A bit conservative because a store completion may not free up entries,
|
|
|
|
// but hopefully avoids two store completions in one cycle from making
|
|
|
|
// the CPU tick twice.
|
2006-10-02 17:58:09 +02:00
|
|
|
cpu->wakeCPU();
|
2006-04-23 00:26:48 +02:00
|
|
|
cpu->activityThisCycle();
|
|
|
|
|
|
|
|
if (store_idx == storeHead) {
|
|
|
|
do {
|
|
|
|
incrStIdx(storeHead);
|
|
|
|
|
|
|
|
--stores;
|
|
|
|
} while (storeQueue[storeHead].completed &&
|
|
|
|
storeHead != storeTail);
|
|
|
|
|
|
|
|
iewStage->updateLSQNextCycle = true;
|
|
|
|
}
|
|
|
|
|
2006-05-19 21:53:17 +02:00
|
|
|
DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head "
|
|
|
|
"idx:%i\n",
|
|
|
|
storeQueue[store_idx].inst->seqNum, store_idx, storeHead);
|
2006-04-23 00:26:48 +02:00
|
|
|
|
|
|
|
if (isStalled() &&
|
|
|
|
storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
|
|
|
|
DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
|
|
|
|
"load idx:%i\n",
|
|
|
|
stallingStoreIsn, stallingLoadIdx);
|
|
|
|
stalled = false;
|
|
|
|
stallingStoreIsn = 0;
|
|
|
|
iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
|
|
|
|
}
|
2006-05-16 20:06:35 +02:00
|
|
|
|
|
|
|
storeQueue[store_idx].inst->setCompleted();
|
2006-05-19 21:53:17 +02:00
|
|
|
|
|
|
|
// Tell the checker we've completed this instruction. Some stores
|
|
|
|
// may get reported twice to the checker, but the checker can
|
|
|
|
// handle that case.
|
2006-06-16 23:08:47 +02:00
|
|
|
#if USE_CHECKER
|
2006-05-16 20:06:35 +02:00
|
|
|
if (cpu->checker) {
|
2006-06-16 19:10:47 +02:00
|
|
|
cpu->checker->verify(storeQueue[store_idx].inst);
|
2006-05-16 20:06:35 +02:00
|
|
|
}
|
2006-06-16 23:08:47 +02:00
|
|
|
#endif
|
2006-04-23 00:26:48 +02:00
|
|
|
}
|
|
|
|
|
2006-06-09 17:46:35 +02:00
|
|
|
template <class Impl>
|
|
|
|
void
|
|
|
|
LSQUnit<Impl>::recvRetry()
|
|
|
|
{
|
|
|
|
if (isStoreBlocked) {
|
2007-08-22 01:16:56 +02:00
|
|
|
DPRINTF(LSQUnit, "Receiving retry: store blocked\n");
|
2006-06-09 22:28:17 +02:00
|
|
|
assert(retryPkt != NULL);
|
|
|
|
|
|
|
|
if (dcachePort->sendTiming(retryPkt)) {
|
|
|
|
storePostSend(retryPkt);
|
2006-06-09 23:21:37 +02:00
|
|
|
retryPkt = NULL;
|
2006-06-09 17:46:35 +02:00
|
|
|
isStoreBlocked = false;
|
2006-08-16 21:56:22 +02:00
|
|
|
lsq->setRetryTid(-1);
|
2006-06-09 17:46:35 +02:00
|
|
|
} else {
|
|
|
|
// Still blocked!
|
2006-06-14 04:35:05 +02:00
|
|
|
++lsqCacheBlocked;
|
2006-07-13 19:12:51 +02:00
|
|
|
lsq->setRetryTid(lsqID);
|
2006-06-09 17:46:35 +02:00
|
|
|
}
|
|
|
|
} else if (isLoadBlocked) {
|
|
|
|
DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, "
|
|
|
|
"no need to resend packet.\n");
|
|
|
|
} else {
|
|
|
|
DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-04-23 00:26:48 +02:00
|
|
|
template <class Impl>
|
|
|
|
inline void
|
|
|
|
LSQUnit<Impl>::incrStIdx(int &store_idx)
|
|
|
|
{
|
|
|
|
if (++store_idx >= SQEntries)
|
|
|
|
store_idx = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
template <class Impl>
|
|
|
|
inline void
|
|
|
|
LSQUnit<Impl>::decrStIdx(int &store_idx)
|
|
|
|
{
|
|
|
|
if (--store_idx < 0)
|
|
|
|
store_idx += SQEntries;
|
|
|
|
}
|
|
|
|
|
|
|
|
template <class Impl>
|
|
|
|
inline void
|
|
|
|
LSQUnit<Impl>::incrLdIdx(int &load_idx)
|
|
|
|
{
|
|
|
|
if (++load_idx >= LQEntries)
|
|
|
|
load_idx = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
template <class Impl>
|
|
|
|
inline void
|
|
|
|
LSQUnit<Impl>::decrLdIdx(int &load_idx)
|
|
|
|
{
|
|
|
|
if (--load_idx < 0)
|
|
|
|
load_idx += LQEntries;
|
|
|
|
}
|
2006-05-19 21:53:17 +02:00
|
|
|
|
|
|
|
template <class Impl>
|
|
|
|
void
|
|
|
|
LSQUnit<Impl>::dumpInsts()
|
|
|
|
{
|
|
|
|
cprintf("Load store queue: Dumping instructions.\n");
|
|
|
|
cprintf("Load queue size: %i\n", loads);
|
|
|
|
cprintf("Load queue: ");
|
|
|
|
|
|
|
|
int load_idx = loadHead;
|
|
|
|
|
|
|
|
while (load_idx != loadTail && loadQueue[load_idx]) {
|
|
|
|
cprintf("%#x ", loadQueue[load_idx]->readPC());
|
|
|
|
|
|
|
|
incrLdIdx(load_idx);
|
|
|
|
}
|
|
|
|
|
|
|
|
cprintf("Store queue size: %i\n", stores);
|
|
|
|
cprintf("Store queue: ");
|
|
|
|
|
|
|
|
int store_idx = storeHead;
|
|
|
|
|
|
|
|
while (store_idx != storeTail && storeQueue[store_idx].inst) {
|
|
|
|
cprintf("%#x ", storeQueue[store_idx].inst->readPC());
|
|
|
|
|
|
|
|
incrStIdx(store_idx);
|
|
|
|
}
|
|
|
|
|
|
|
|
cprintf("\n");
|
|
|
|
}
|