xv6-cs450/main.c

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#include "types.h"
#include "param.h"
#include "mmu.h"
#include "proc.h"
#include "defs.h"
#include "x86.h"
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#include "traps.h"
#include "syscall.h"
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#include "elf.h"
#include "param.h"
#include "spinlock.h"
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extern char edata[], end[];
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// Bootstrap processor starts running C code here.
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// This is called main0 not main so that it can have
// a void return type. Gcc can't handle functions named
// main that don't return int. Really.
void
main0(void)
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{
int i;
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static int bcpu; // cannot be on stack
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// clear BSS
memset(edata, 0, end - edata);
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// Prevent release() from enabling interrupts.
for(i=0; i<NCPU; i++)
cpus[i].nlock = 1;
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mp_init(); // collect info about this machine
bcpu = mp_bcpu();
// switch to bootstrap processor's stack
asm volatile("movl %0, %%esp" : : "r" (cpus[bcpu].mpstack+MPSTACK-32));
asm volatile("movl %0, %%ebp" : : "r" (cpus[bcpu].mpstack+MPSTACK));
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lapic_init(bcpu);
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cprintf("\ncpu%d: starting xv6\n\n", cpu());
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pinit(); // process table
binit(); // buffer cache
pic_init(); // interrupt controller
ioapic_init(); // another interrupt controller
kinit(); // physical memory allocator
tvinit(); // trap vectors
idtinit(); // interrupt descriptor table
fileinit(); // file table
iinit(); // inode cache
setupsegs(0); // segments & TSS
console_init(); // I/O devices & their interrupts
ide_init(); // disk
mp_startthem(); // other CPUs
if(ismp){
lapic_timerinit(); // smp timer
lapic_enableintr(); // local interrupts
}else
pit8253_timerinit(); // uniprocessor timer
userinit(); // first user process
// enable interrupts on this processor.
cpus[cpu()].nlock--;
sti();
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scheduler();
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}
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// Additional processors start here.
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void
mpmain(void)
{
cprintf("cpu%d: starting\n", cpu());
idtinit(); // CPU's idt
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if(cpu() == 0)
panic("mpmain on cpu 0");
lapic_init(cpu());
lapic_timerinit();
lapic_enableintr();
// make sure there's a TSS
setupsegs(0);
cpuid(0, 0, 0, 0, 0); // memory barrier
cpus[cpu()].booted = 1;
// Enable interrupts on this processor.
cpus[cpu()].nlock--;
sti();
scheduler();
}