Commit graph

16 commits

Author SHA1 Message Date
Kees Jongenburger
2830a5af5c arm:perform copy operation using same cacheability.
When copying data from cacheable memory also use cacheable
attributes when creating temporary mappings.

Change-Id: I0e8380293fb4edaafba49f6262983ad86a5350c5
2013-09-26 11:54:36 +02:00
Kees Jongenburger
0d02dc9d54 arm:make the MMU fetch pagetable data through the caches.
Change-Id: Ibd7b66558c369d0c0792c02801562580d255fa1f
2013-09-26 11:54:36 +02:00
Kees Jongenburger
b98441772c arm:vm map free running clock uncached. 2013-09-26 09:08:13 +02:00
Kees Jongenburger
a88bc73e4c arm:allow to lookup physical addresses of sections.
Change-Id: If4716b81cceee5d8b30d5f103b772b0ac99fc807
2013-09-26 09:07:36 +02:00
Kees Jongenburger
b1a7d4d7ea arm:misc fix remove const modifier for value that changes.
Change-Id: I4ac96acdc66ea203a339108225c07c68959556c0
2013-09-26 09:06:24 +02:00
Ben Gras
5bc48ef12e kernel, libsys: make it arm-target-independent
. by making the address and frequency of the
	  free running clock kinfo members, set at runtime
	  in the kernel, instead of compile time constants
	  in libsys

Change-Id: I4a8387302d4d3ffd47d2448525725683a74c9a4f
2013-06-17 09:55:36 +02:00
Kees Jongenburger
a2fcba659c arm:remove pre 1:1 mapping workarounds.
Change-Id: I5a690cf5a561cdca9b9c1f031402f80fd203c92d
2013-06-12 16:42:20 +02:00
Kees Jongenburger
a5a693a046 arm:no longer rely on a 1:1 phys mapping for device memory.
Change-Id: Ie3f61069f882c37dbb81dee813fdfd883e7468cf
2013-06-12 16:42:12 +02:00
Kees Jongenburger
3139ce9631 arm:omap timers remove hardcoded base address.
Omap timers remove hardcoded base address and add some initial
support for the beaglebone's timers. Frclock_util will need
refactoring to remain independent of the ARM flavour.

Change-Id: I2b5d04e930364262c81b5686de634c0a51796b23
2013-05-24 14:03:14 +02:00
Kees Jongenburger
1e1ff96aea arm:vm caching fix.
Improve reliability by using write trough cache.
2013-05-16 20:39:20 +02:00
Kees Jongenburger
e6bac75a8b ARM:Rename ARM_BIG_PAGE to ARM_SECTION.
The natural term to use when talking about MINIX big pages on ARM
is SECTION. A section is a level 1 page table entry pointing to
a 1MB area.

Change-Id: I9bd27ca99bc772126c31c27a537b1415db20c4a6
2013-04-29 11:42:26 +02:00
Ben Gras
2aa82a9c7b ARM: kernel: fix sanity check for copying
. phys_copy() (taken from memcpy) can legitimately
	  cause pagefaults below the source/dest address due
	  to word-alignment

Change-Id: Ibee8f069781d16caea671246c021fb17a2a892b1
2013-02-20 20:34:40 +01:00
Lionel Sambuc
e4fa9802cb ARM: Enable caches
First round, some more optimizations are possible and should be
activated.

Change-Id: I3b7dee7c82fbffd823a08bec1c5d5ebcf769f92f
2013-02-18 09:08:26 +01:00
Ben Gras
8ea66915f2 kernel: scheduling fix for ARM
. make read_tsc_64 use the free-running clock, significantly
	  improving scheduling behaviour

Change-Id: Idf6a12f6e26be7fe3b3664c278cae846d8b2a442
2013-02-03 22:49:05 +01:00
Thomas Veerman
db8c1ee9d0 ARM: provide free running clock to replace ccnt
The Cycle CouNTer on ARM cannot be used reliably as it wraps around
rather quickly and can be altered by user space (on Minix). Furthermore,
it's buggy when wrapping and is not implemented at all on the Linaro
Beagleboard emulator.

This patch programs GPTIMER10 as a free running clock at 1.625 MHz (it
doesn't generate interrupts). It's memory mapped into every process,
which enables libsys to provide micro_delay().

Change-Id: Iba004c6c62976762fe154ea390d69e518eec1531
2013-01-31 15:19:11 +00:00
Lionel Sambuc
b1c4ba4ab6 ARM updates
Due to the ABI we are using we have to use the earm architecture
moniker for the build system to behave correctly. This involves
then some headers to move around.

There is also a few related Makefile updates as well as minor
source code corrections.
2013-01-17 10:03:58 +01:00
Renamed from kernel/arch/arm/memory.c (Browse further)