arm:omap timers remove hardcoded base address.
Omap timers remove hardcoded base address and add some initial support for the beaglebone's timers. Frclock_util will need refactoring to remain independent of the ARM flavour. Change-Id: I2b5d04e930364262c81b5686de634c0a51796b23
This commit is contained in:
Kees Jongenburger
parent
534b19187e
commit
3139ce9631
4 changed files with 331 additions and 93 deletions
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@ -29,7 +29,6 @@ static int freepdes[MAXFREEPDES];
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static u32_t phys_get32(phys_bytes v);
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extern vir_bytes omap3_gptimer10_base = OMAP3_GPTIMER10_BASE;
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void mem_clear_mapcache(void)
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{
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@ -726,14 +725,28 @@ int arch_phys_map(const int index,
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return OK;
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}
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else if (index == device_mem_mapping_index) {
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#ifdef DM37XX
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/* map device memory */
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*addr = 0x48000000;
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*len = 0x02000000;
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#endif
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#ifdef AM335X
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/* map device memory until 0x5700 SGX */
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*addr = 0x44000000;
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*len = 0x06000000;
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#endif
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*flags = VMMF_UNCACHED | VMMF_WRITE;
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return OK;
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}
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else if (index == frclock_index) {
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#ifdef DM37XX
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*addr = OMAP3_GPTIMER10_BASE;
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#endif
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#ifdef AM335X
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*addr = AM335X_DMTIMER7_BASE;
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#endif
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*len = ARM_PAGE_SIZE;
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*flags = VMMF_USER;
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return OK;
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@ -774,7 +787,13 @@ int arch_phys_map_reply(const int index, const vir_bytes addr)
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return OK;
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}
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else if (index == frclock_index) {
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omap3_gptimer10_base = minix_kerninfo.minix_frclock = addr;
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#ifdef DM37XX
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minix_kerninfo.minix_frclock = addr;
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#endif
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#ifdef AM335X
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minix_kerninfo.minix_frclock = addr;
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#endif
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return OK;
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}
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@ -2,7 +2,10 @@
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#include "kernel/clock.h"
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#include <sys/types.h>
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#include <machine/cpu.h>
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#include <minix/mmio.h>
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#include <io.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include "arch_proto.h"
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#include "omap_timer.h"
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#include "omap_intr.h"
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@ -10,15 +13,130 @@
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static irq_hook_t omap3_timer_hook; /* interrupt handler hook */
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static u64_t high_frc;
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vir_bytes omap3_gptimer10_base;
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struct omap_timer_registers;
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struct omap_timer {
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vir_bytes base;
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int irq_nr;
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struct omap_timer_registers *regs;
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};
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struct omap_timer_registers {
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vir_bytes TIDR;
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vir_bytes TIOCP_CFG;
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vir_bytes TISTAT;
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vir_bytes TISR;
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vir_bytes TIER;
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vir_bytes TWER;
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vir_bytes TCLR;
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vir_bytes TCRR;
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vir_bytes TLDR;
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vir_bytes TTGR;
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vir_bytes TWPS;
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vir_bytes TMAR;
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vir_bytes TCAR1;
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vir_bytes TSICR;
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vir_bytes TCAR2;
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vir_bytes TPIR;
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vir_bytes TNIR;
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vir_bytes TCVR;
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vir_bytes TOCR;
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vir_bytes TOWR;
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};
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static struct omap_timer_registers regs_v1 = {
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.TIDR = OMAP3_TIMER_TIDR,
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.TIOCP_CFG = OMAP3_TIMER_TIOCP_CFG,
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.TISTAT = OMAP3_TIMER_TISTAT,
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.TISR = OMAP3_TIMER_TISR,
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.TIER = OMAP3_TIMER_TIER,
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.TWER = OMAP3_TIMER_TWER,
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.TCLR = OMAP3_TIMER_TCLR,
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.TCRR = OMAP3_TIMER_TCRR,
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.TLDR = OMAP3_TIMER_TLDR,
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.TTGR = OMAP3_TIMER_TTGR,
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.TWPS = OMAP3_TIMER_TWPS,
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.TMAR = OMAP3_TIMER_TMAR,
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.TCAR1 = OMAP3_TIMER_TCAR1,
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.TSICR = OMAP3_TIMER_TSICR,
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.TCAR2 = OMAP3_TIMER_TCAR2,
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.TPIR = OMAP3_TIMER_TPIR,
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.TNIR = OMAP3_TIMER_TNIR,
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.TCVR = OMAP3_TIMER_TCVR,
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.TOCR = OMAP3_TIMER_TOCR,
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.TOWR = OMAP3_TIMER_TOWR,
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};
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#ifdef DM37XX
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static struct omap_timer timer = {
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.base = OMAP3_GPTIMER1_BASE,
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.irq_nr = OMAP3_GPT1_IRQ,
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.regs = ®s_v1
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};
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/* free running timer */
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static struct omap_timer fr_timer = {
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.base = OMAP3_GPTIMER10_BASE,
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.irq_nr = OMAP3_GPT10_IRQ,
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.regs = ®s_v1
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};
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#endif
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#ifdef AM335X
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/* AM335X has a different ip block for the non
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1ms timers */
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static struct omap_timer_registers regs_v2 = {
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.TIDR = AM335X_TIMER_TIDR,
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.TIOCP_CFG = AM335X_TIMER_TIOCP_CFG,
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.TISTAT = AM335X_TIMER_IRQSTATUS_RAW,
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.TISR = AM335X_TIMER_IRQSTATUS,
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.TIER = AM335X_TIMER_IRQENABLE_SET,
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.TWER = AM335X_TIMER_IRQWAKEEN,
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.TCLR = AM335X_TIMER_TCLR,
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.TCRR = AM335X_TIMER_TCRR,
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.TLDR = AM335X_TIMER_TLDR,
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.TTGR = AM335X_TIMER_TTGR,
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.TWPS = AM335X_TIMER_TWPS,
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.TMAR = AM335X_TIMER_TMAR,
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.TCAR1 = AM335X_TIMER_TCAR1,
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.TSICR = AM335X_TIMER_TSICR,
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.TCAR2 = AM335X_TIMER_TCAR2,
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.TPIR = -1 , /* UNDEF */
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.TNIR = -1 , /* UNDEF */
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.TCVR = -1 , /* UNDEF */
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.TOCR = -1 , /* UNDEF */
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.TOWR = -1 /* UNDEF */
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};
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/* normal timer */
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static struct omap_timer timer = {
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.base = AM335X_DMTIMER1_1MS_BASE,
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.irq_nr = AM335X_INT_TINT1_1MS,
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.regs = ®s_v1
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};
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/* free running timer */
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static struct omap_timer fr_timer = {
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.base = AM335X_DMTIMER7_BASE,
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.irq_nr = AM335X_INT_TINT7,
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.regs = ®s_v2
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};
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#endif
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static int done = 0;
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int omap3_register_timer_handler(const irq_handler_t handler)
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{
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/* Initialize the CLOCK's interrupt hook. */
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omap3_timer_hook.proc_nr_e = NONE;
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omap3_timer_hook.irq = OMAP3_GPT1_IRQ;
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omap3_timer_hook.irq = timer.irq_nr;
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put_irq_handler(&omap3_timer_hook, OMAP3_GPT1_IRQ, handler);
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put_irq_handler(&omap3_timer_hook, timer.irq_nr, handler);
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return 0;
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}
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@ -27,75 +145,113 @@ void omap3_frclock_init(void)
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{
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u32_t tisr;
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/* Stop timer */
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mmio_clear(OMAP3_GPTIMER10_TCLR, OMAP3_TCLR_ST);
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/* enable the clock */
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#ifdef AM335X
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/* Disable the module and wait for the module to be disabled */
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set32(CM_PER_TIMER7_CLKCTRL, CM_MODULEMODE_MASK,CM_MODULEMODE_DISABLED);
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while( (mmio_read(CM_PER_TIMER7_CLKCTRL) & CM_CLKCTRL_IDLEST) != CM_CLKCTRL_IDLEST_DISABLE);
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set32(CLKSEL_TIMER7_CLK,CLKSEL_TIMER7_CLK_SEL_MASK, CLKSEL_TIMER7_CLK_SEL_SEL2);
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while( (read32(CLKSEL_TIMER7_CLK) & CLKSEL_TIMER7_CLK_SEL_MASK) != CLKSEL_TIMER7_CLK_SEL_SEL2);
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/* enable the module and wait for the module to be ready */
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set32(CM_PER_TIMER7_CLKCTRL,CM_MODULEMODE_MASK,CM_MODULEMODE_ENABLE);
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while( (mmio_read(CM_PER_TIMER7_CLKCTRL) & CM_CLKCTRL_IDLEST) != CM_CLKCTRL_IDLEST_FUNC);
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#endif
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/* Stop timer */
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mmio_clear(fr_timer.base + fr_timer.regs->TCLR, OMAP3_TCLR_ST);
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#ifdef DM37XX
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/* Use functional clock source for GPTIMER10 */
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mmio_set(OMAP3_CM_CLKSEL_CORE, OMAP3_CLKSEL_GPT10);
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#endif
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#ifdef DM37XX
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/* Scale timer down to 13/8 = 1.625 Mhz to roughly get microsecond ticks */
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/* The scale is computed as 2^(PTV+1). So if PTV == 2, we get 2^3 = 8.
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*/
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mmio_set(OMAP3_GPTIMER10_TCLR, (2 << OMAP3_TCLR_PTV));
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mmio_set(fr_timer.base + fr_timer.regs->TCLR, (2 << OMAP3_TCLR_PTV));
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#endif
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#ifdef AM335X
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/* 24Mhz / 16 = 1.5 Mhz */
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mmio_set(fr_timer.base + fr_timer.regs->TCLR, (3 << OMAP3_TCLR_PTV));
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#endif
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/* Start and auto-reload at 0 */
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mmio_write(OMAP3_GPTIMER10_TLDR, 0x0);
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mmio_write(OMAP3_GPTIMER10_TCRR, 0x0);
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mmio_write(fr_timer.base + fr_timer.regs->TLDR, 0x0);
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mmio_write(fr_timer.base + fr_timer.regs->TCRR, 0x0);
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/* Set up overflow interrupt */
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tisr = OMAP3_TISR_MAT_IT_FLAG | OMAP3_TISR_OVF_IT_FLAG |
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OMAP3_TISR_TCAR_IT_FLAG;
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mmio_write(OMAP3_GPTIMER10_TISR, tisr); /* Clear interrupt status */
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mmio_write(OMAP3_GPTIMER10_TIER, OMAP3_TIER_OVF_IT_ENA);
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mmio_write(fr_timer.base + fr_timer.regs->TISR, tisr); /* Clear interrupt status */
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mmio_write(fr_timer.base + fr_timer.regs->TIER, OMAP3_TIER_OVF_IT_ENA);
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/* Start timer */
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mmio_set(OMAP3_GPTIMER10_TCLR,
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mmio_set(fr_timer.base + fr_timer.regs->TCLR,
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OMAP3_TCLR_OVF_TRG|OMAP3_TCLR_AR|OMAP3_TCLR_ST|OMAP3_TCLR_PRE);
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}
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void omap3_frclock_stop()
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{
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mmio_clear(OMAP3_GPTIMER10_TCLR, OMAP3_TCLR_ST);
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mmio_clear(fr_timer.base + fr_timer.regs->TCLR, OMAP3_TCLR_ST);
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}
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void omap3_timer_init(unsigned freq)
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{
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u32_t tisr;
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#ifdef AM335X
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/* disable the module and wait for the module to be disabled */
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set32(CM_WKUP_TIMER1_CLKCTRL, CM_MODULEMODE_MASK,CM_MODULEMODE_DISABLED);
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while( (mmio_read(CM_WKUP_TIMER1_CLKCTRL) & CM_CLKCTRL_IDLEST) != CM_CLKCTRL_IDLEST_DISABLE);
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set32(CLKSEL_TIMER1MS_CLK,CLKSEL_TIMER1MS_CLK_SEL_MASK, CLKSEL_TIMER1MS_CLK_SEL_SEL2);
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while( (read32(CLKSEL_TIMER1MS_CLK) & CLKSEL_TIMER1MS_CLK_SEL_MASK) != CLKSEL_TIMER1MS_CLK_SEL_SEL2);
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/* enable the module and wait for the module to be ready */
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set32(CM_WKUP_TIMER1_CLKCTRL,CM_MODULEMODE_MASK,CM_MODULEMODE_ENABLE);
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while( (mmio_read(CM_WKUP_TIMER1_CLKCTRL) & CM_CLKCTRL_IDLEST) != CM_CLKCTRL_IDLEST_FUNC);
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#endif
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/* Stop timer */
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mmio_clear(OMAP3_GPTIMER1_TCLR, OMAP3_TCLR_ST);
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mmio_clear(timer.base + fr_timer.regs->TCLR, OMAP3_TCLR_ST);
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#ifdef DM37XX
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/* Use 32 KHz clock source for GPTIMER1 */
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mmio_clear(OMAP3_CM_CLKSEL_WKUP, OMAP3_CLKSEL_GPT1);
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#endif
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/* Use 1-ms tick mode for GPTIMER1 TRM 16.2.4.2.1 */
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mmio_write(OMAP3_GPTIMER1_TPIR, 232000);
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mmio_write(OMAP3_GPTIMER1_TNIR, -768000);
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mmio_write(OMAP3_GPTIMER1_TLDR, 0xffffffe0);
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mmio_write(OMAP3_GPTIMER1_TCRR, 0xffffffe0);
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mmio_write(timer.base + timer.regs->TPIR, 232000);
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mmio_write(timer.base + timer.regs->TNIR, -768000);
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mmio_write(timer.base + timer.regs->TLDR, 0xffffffe0);
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mmio_write(timer.base + timer.regs->TCRR, 0xffffffe0);
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/* Set up overflow interrupt */
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tisr = OMAP3_TISR_MAT_IT_FLAG | OMAP3_TISR_OVF_IT_FLAG |
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OMAP3_TISR_TCAR_IT_FLAG;
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mmio_write(OMAP3_GPTIMER1_TISR, tisr); /* Clear interrupt status */
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mmio_write(OMAP3_GPTIMER1_TIER, OMAP3_TIER_OVF_IT_ENA);
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omap3_irq_unmask(OMAP3_GPT1_IRQ);
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mmio_write(timer.base + timer.regs->TISR, tisr); /* Clear interrupt status */
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mmio_write(timer.base + timer.regs->TIER, OMAP3_TIER_OVF_IT_ENA);
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omap3_irq_unmask(timer.irq_nr);
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/* Start timer */
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mmio_set(OMAP3_GPTIMER1_TCLR,
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mmio_set(timer.base + timer.regs->TCLR,
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OMAP3_TCLR_OVF_TRG|OMAP3_TCLR_AR|OMAP3_TCLR_ST);
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}
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void omap3_timer_stop()
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{
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mmio_clear(OMAP3_GPTIMER1_TCLR, OMAP3_TCLR_ST);
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mmio_clear(timer.base + timer.regs->TCLR, OMAP3_TCLR_ST);
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}
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static u32_t read_frc(void)
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{
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u32_t frc = *(u32_t *) ((char *) omap3_gptimer10_base + OMAP3_TCRR);
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return frc;
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if (done == 0)
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return 0;
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return mmio_read(fr_timer.base + fr_timer.regs->TCRR);
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}
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static void frc_overflow_check(void)
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@ -114,9 +270,14 @@ void omap3_timer_int_handler()
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/* Clear all interrupts */
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u32_t tisr;
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/* when the kernel itself is running interrupts are disabled.
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* We should therefore also read the overflow counter to detect
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* this as to not miss events.
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*/
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tisr = OMAP3_TISR_MAT_IT_FLAG | OMAP3_TISR_OVF_IT_FLAG |
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OMAP3_TISR_TCAR_IT_FLAG;
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mmio_write(OMAP3_GPTIMER1_TISR, tisr);
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mmio_write(timer.base + timer.regs->TISR, tisr);
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frc_overflow_check();
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}
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@ -1,6 +1,8 @@
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#ifndef _OMAP_TIMER_REGISTERS_H
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#define _OMAP_TIMER_REGISTERS_H
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#ifdef DM37XX
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/* General-purpose timer register map */
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#define OMAP3_GPTIMER1_BASE 0x48318000 /* GPTIMER1 physical address */
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#define OMAP3_GPTIMER2_BASE 0x49032000 /* GPTIMER2 physical address */
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@ -14,27 +16,60 @@
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#define OMAP3_GPTIMER10_BASE 0x48086000 /* GPTIMER10 physical address */
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#define OMAP3_GPTIMER11_BASE 0x48088000 /* GPTIMER11 physical address */
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#endif /* DM37XX */
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/* General-purpose timer registers */
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#define OMAP3_TIDR 0x000 /* IP revision code */
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#define OMAP3_TIOCP_CFG 0x010 /* Controls params for GP timer L4 interface */
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#define OMAP3_TISTAT 0x014 /* Status (excl. interrupt status) */
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#define OMAP3_TISR 0x018 /* Pending interrupt status */
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#define OMAP3_TIER 0x01C /* Interrupt enable */
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#define OMAP3_TWER 0x020 /* Wakeup enable */
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#define OMAP3_TCLR 0x024 /* Controls optional features */
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#define OMAP3_TCRR 0x028 /* Internal counter value */
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#define OMAP3_TLDR 0x02C /* Timer load value */
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#define OMAP3_TTGR 0x030 /* Triggers counter reload */
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#define OMAP3_TWPS 0x034 /* Indicates if Write-Posted pending */
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#define OMAP3_TMAR 0x038 /* Value to be compared with counter */
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#define OMAP3_TCAR1 0x03C /* First captured value of counter register */
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#define OMAP3_TSICR 0x040 /* Control posted mode and functional SW reset */
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#define OMAP3_TCAR2 0x044 /* Second captured value of counter register */
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#define OMAP3_TPIR 0x048 /* Positive increment (1 ms tick) */
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#define OMAP3_TNIR 0x04C /* Negative increment (1 ms tick) */
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#define OMAP3_TCVR 0x050 /* Defines TCRR is sub/over-period (1 ms tick) */
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#define OMAP3_TOCR 0x054 /* Masks tick interrupt */
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#define OMAP3_TOWR 0x058 /* Number of masked overflow interrupts */
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#define OMAP3_TIMER_TIDR 0x000 /* IP revision code */
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#define OMAP3_TIMER_TIOCP_CFG 0x010 /* Controls params for GP timer L4 interface */
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#define OMAP3_TIMER_TISTAT 0x014 /* Status (excl. interrupt status) */
|
||||
#define OMAP3_TIMER_TISR 0x018 /* Pending interrupt status */
|
||||
#define OMAP3_TIMER_TIER 0x01C /* Interrupt enable */
|
||||
#define OMAP3_TIMER_TWER 0x020 /* Wakeup enable */
|
||||
#define OMAP3_TIMER_TCLR 0x024 /* Controls optional features */
|
||||
#define OMAP3_TIMER_TCRR 0x028 /* Internal counter value */
|
||||
#define OMAP3_TIMER_TLDR 0x02C /* Timer load value */
|
||||
#define OMAP3_TIMER_TTGR 0x030 /* Triggers counter reload */
|
||||
#define OMAP3_TIMER_TWPS 0x034 /* Indicates if Write-Posted pending */
|
||||
#define OMAP3_TIMER_TMAR 0x038 /* Value to be compared with counter */
|
||||
#define OMAP3_TIMER_TCAR1 0x03C /* First captured value of counter register */
|
||||
#define OMAP3_TIMER_TSICR 0x040 /* Control posted mode and functional SW reset */
|
||||
#define OMAP3_TIMER_TCAR2 0x044 /* Second captured value of counter register */
|
||||
#define OMAP3_TIMER_TPIR 0x048 /* Positive increment (1 ms tick) */
|
||||
#define OMAP3_TIMER_TNIR 0x04C /* Negative increment (1 ms tick) */
|
||||
#define OMAP3_TIMER_TCVR 0x050 /* Defines TCRR is sub/over-period (1 ms tick) */
|
||||
#define OMAP3_TIMER_TOCR 0x054 /* Masks tick interrupt */
|
||||
#define OMAP3_TIMER_TOWR 0x058 /* Number of masked overflow interrupts */
|
||||
|
||||
#ifdef AM335X
|
||||
#define AM335X_DMTIMER0_BASE 0x44E05000 /* DMTimer0 Registers */
|
||||
#define AM335X_DMTIMER1_1MS_BASE 0x44E31000 /* DMTimer1 1ms Registers (Accurate 1ms timer) */
|
||||
#define AM335X_DMTIMER2_BASE 0x48040000 /* DMTimer2 Registers */
|
||||
#define AM335X_DMTIMER3_BASE 0x48042000 /* DMTimer3 Registers */
|
||||
#define AM335X_DMTIMER4_BASE 0x48044000 /* DMTimer4 Registers */
|
||||
#define AM335X_DMTIMER5_BASE 0x48046000 /* DMTimer5 Registers */
|
||||
#define AM335X_DMTIMER6_BASE 0x48048000 /* DMTimer6 Registers */
|
||||
#define AM335X_DMTIMER7_BASE 0x4804A000 /* DMTimer7 Registers */
|
||||
|
||||
/* General-purpose timer registers AM335x non 1MS timers have different offsets */
|
||||
#define AM335X_TIMER_TIDR 0x000 /* IP revision code */
|
||||
#define AM335X_TIMER_TIOCP_CFG 0x010 /* Controls params for GP timer L4 interface */
|
||||
#define AM335X_TIMER_IRQSTATUS_RAW 0x024 /* Timer IRQSTATUS Raw Register */
|
||||
#define AM335X_TIMER_IRQSTATUS 0x028 /* Timer IRQSTATUS Register */
|
||||
#define AM335X_TIMER_IRQENABLE_SET 0x02C /* Timer IRQENABLE Set Register */
|
||||
#define AM335X_TIMER_IRQENABLE_CLR 0x030 /* Timer IRQENABLE Clear Register */
|
||||
#define AM335X_TIMER_IRQWAKEEN 0x034 /* Timer IRQ Wakeup Enable Register */
|
||||
#define AM335X_TIMER_TCLR 0x038 /* Controls optional features */
|
||||
#define AM335X_TIMER_TCRR 0x03C /* Internal counter value */
|
||||
#define AM335X_TIMER_TLDR 0x040 /* Timer load value */
|
||||
#define AM335X_TIMER_TTGR 0x044 /* Triggers counter reload */
|
||||
#define AM335X_TIMER_TWPS 0x048 /* Indicates if Write-Posted pending */
|
||||
#define AM335X_TIMER_TMAR 0x04C /* Value to be compared with counter */
|
||||
#define AM335X_TIMER_TCAR1 0x050 /* First captured value of counter register */
|
||||
#define AM335X_TIMER_TSICR 0x054 /* Control posted mode and functional SW reset */
|
||||
#define AM335X_TIMER_TCAR2 0x058 /* Second captured value of counter register */
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/* Interrupt status register fields */
|
||||
#define OMAP3_TISR_MAT_IT_FLAG (1 << 0) /* Pending match interrupt status */
|
||||
|
|
@ -50,58 +85,68 @@
|
|||
#define OMAP3_TCLR_ST (1 << 0) /* Start/stop timer */
|
||||
#define OMAP3_TCLR_AR (1 << 1) /* Autoreload or one-shot mode */
|
||||
#define OMAP3_TCLR_PRE (1 << 5) /* Prescaler on */
|
||||
#define OMAP3_TCLR_PTV 2
|
||||
#define OMAP3_TCLR_PTV 2
|
||||
#define OMAP3_TCLR_OVF_TRG (1 << 10) /* Overflow trigger */
|
||||
|
||||
#define OMAP3_GPTIMER1_TIDR (OMAP3_GPTIMER1_BASE + OMAP3_TIDR)
|
||||
#define OMAP3_GPTIMER1_TIOCP_CFG (OMAP3_GPTIMER1_BASE + OMAP3_TIOCP_CFG)
|
||||
#define OMAP3_GPTIMER1_TISTAT (OMAP3_GPTIMER1_BASE + OMAP3_TISTAT)
|
||||
#define OMAP3_GPTIMER1_TISR (OMAP3_GPTIMER1_BASE + OMAP3_TISR)
|
||||
#define OMAP3_GPTIMER1_TIER (OMAP3_GPTIMER1_BASE + OMAP3_TIER)
|
||||
#define OMAP3_GPTIMER1_TWER (OMAP3_GPTIMER1_BASE + OMAP3_TWER)
|
||||
#define OMAP3_GPTIMER1_TCLR (OMAP3_GPTIMER1_BASE + OMAP3_TCLR)
|
||||
#define OMAP3_GPTIMER1_TCRR (OMAP3_GPTIMER1_BASE + OMAP3_TCRR)
|
||||
#define OMAP3_GPTIMER1_TLDR (OMAP3_GPTIMER1_BASE + OMAP3_TLDR)
|
||||
#define OMAP3_GPTIMER1_TTGR (OMAP3_GPTIMER1_BASE + OMAP3_TTGR)
|
||||
#define OMAP3_GPTIMER1_TWPS (OMAP3_GPTIMER1_BASE + OMAP3_TWPS)
|
||||
#define OMAP3_GPTIMER1_TMAR (OMAP3_GPTIMER1_BASE + OMAP3_TMAR)
|
||||
#define OMAP3_GPTIMER1_TCAR1 (OMAP3_GPTIMER1_BASE + OMAP3_TCAR1)
|
||||
#define OMAP3_GPTIMER1_TSICR (OMAP3_GPTIMER1_BASE + OMAP3_TSICR)
|
||||
#define OMAP3_GPTIMER1_TCAR2 (OMAP3_GPTIMER1_BASE + OMAP3_TCAR2)
|
||||
#define OMAP3_GPTIMER1_TPIR (OMAP3_GPTIMER1_BASE + OMAP3_TPIR)
|
||||
#define OMAP3_GPTIMER1_TNIR (OMAP3_GPTIMER1_BASE + OMAP3_TNIR)
|
||||
#define OMAP3_GPTIMER1_TCVR (OMAP3_GPTIMER1_BASE + OMAP3_TCVR)
|
||||
#define OMAP3_GPTIMER1_TOCR (OMAP3_GPTIMER1_BASE + OMAP3_TOCR)
|
||||
#define OMAP3_GPTIMER1_TOWR (OMAP3_GPTIMER1_BASE + OMAP3_TOWR)
|
||||
|
||||
#define OMAP3_GPTIMER10_TIDR (OMAP3_GPTIMER10_BASE + OMAP3_TIDR)
|
||||
#define OMAP3_GPTIMER10_TIOCP_CFG (OMAP3_GPTIMER10_BASE + OMAP3_TIOCP_CFG)
|
||||
#define OMAP3_GPTIMER10_TISTAT (OMAP3_GPTIMER10_BASE + OMAP3_TISTAT)
|
||||
#define OMAP3_GPTIMER10_TISR (OMAP3_GPTIMER10_BASE + OMAP3_TISR)
|
||||
#define OMAP3_GPTIMER10_TIER (OMAP3_GPTIMER10_BASE + OMAP3_TIER)
|
||||
#define OMAP3_GPTIMER10_TWER (OMAP3_GPTIMER10_BASE + OMAP3_TWER)
|
||||
#define OMAP3_GPTIMER10_TCLR (OMAP3_GPTIMER10_BASE + OMAP3_TCLR)
|
||||
#define OMAP3_GPTIMER10_TCRR (OMAP3_GPTIMER10_BASE + OMAP3_TCRR)
|
||||
#define OMAP3_GPTIMER10_TLDR (OMAP3_GPTIMER10_BASE + OMAP3_TLDR)
|
||||
#define OMAP3_GPTIMER10_TTGR (OMAP3_GPTIMER10_BASE + OMAP3_TTGR)
|
||||
#define OMAP3_GPTIMER10_TWPS (OMAP3_GPTIMER10_BASE + OMAP3_TWPS)
|
||||
#define OMAP3_GPTIMER10_TMAR (OMAP3_GPTIMER10_BASE + OMAP3_TMAR)
|
||||
#define OMAP3_GPTIMER10_TCAR1 (OMAP3_GPTIMER10_BASE + OMAP3_TCAR1)
|
||||
#define OMAP3_GPTIMER10_TSICR (OMAP3_GPTIMER10_BASE + OMAP3_TSICR)
|
||||
#define OMAP3_GPTIMER10_TCAR2 (OMAP3_GPTIMER10_BASE + OMAP3_TCAR2)
|
||||
#define OMAP3_GPTIMER10_TPIR (OMAP3_GPTIMER10_BASE + OMAP3_TPIR)
|
||||
#define OMAP3_GPTIMER10_TNIR (OMAP3_GPTIMER10_BASE + OMAP3_TNIR)
|
||||
#define OMAP3_GPTIMER10_TCVR (OMAP3_GPTIMER10_BASE + OMAP3_TCVR)
|
||||
#define OMAP3_GPTIMER10_TOCR (OMAP3_GPTIMER10_BASE + OMAP3_TOCR)
|
||||
#define OMAP3_GPTIMER10_TOWR (OMAP3_GPTIMER10_BASE + OMAP3_TOWR)
|
||||
#ifdef DM37XX
|
||||
|
||||
#define OMAP3_CM_CLKSEL_GFX 0x48004b40
|
||||
#define OMAP3_CM_CLKEN_PLL 0x48004d00
|
||||
#define OMAP3_CM_FCLKEN1_CORE 0x48004A00
|
||||
#define OMAP3_CM_CLKSEL_CORE 0x48004A40 /* GPT10 src clock sel. */
|
||||
#define OMAP3_CM_FCLKEN1_CORE 0x48004A00
|
||||
#define OMAP3_CM_CLKSEL_CORE 0x48004A40 /* GPT10 src clock sel. */
|
||||
#define OMAP3_CM_FCLKEN_PER 0x48005000
|
||||
#define OMAP3_CM_CLKSEL_PER 0x48005040
|
||||
#define OMAP3_CM_CLKSEL_WKUP 0x48004c40 /* GPT1 source clock selection */
|
||||
#define OMAP3_CM_CLKSEL_WKUP 0x48004c40 /* GPT1 source clock selection */
|
||||
|
||||
#endif /* DM37XX */
|
||||
|
||||
#ifdef AM335X
|
||||
|
||||
#define CM_MODULEMODE_MASK (0x3 << 0)
|
||||
#define CM_MODULEMODE_ENABLE (0x2 << 0)
|
||||
#define CM_MODULEMODE_DISABLED (0x0 << 0)
|
||||
|
||||
#define CM_CLKCTRL_IDLEST (0x3 << 16)
|
||||
#define CM_CLKCTRL_IDLEST_FUNC (0x0 << 16)
|
||||
#define CM_CLKCTRL_IDLEST_TRANS (0x1 << 16)
|
||||
#define CM_CLKCTRL_IDLEST_IDLE (0x2 << 16)
|
||||
#define CM_CLKCTRL_IDLEST_DISABLE (0x3 << 16)
|
||||
|
||||
#define CM_WKUP_BASE 0x44E00400 /* Clock Module Wakeup Registers */
|
||||
|
||||
#define CM_WKUP_TIMER1_CLKCTRL (CM_WKUP_BASE + 0xC4) /* This register manages the TIMER1 clocks. [Memory Mapped] */
|
||||
|
||||
|
||||
#define CM_PER_BASE 0x44E00000 /* Clock Module Peripheral Registers */
|
||||
#define CM_PER_TIMER7_CLKCTRL (CM_PER_BASE + 0x7C) /* This register manages the TIMER7 clocks. [Memory Mapped] */
|
||||
|
||||
|
||||
|
||||
/* CM_DPLL registers */
|
||||
|
||||
|
||||
#define CM_DPLL_BASE 0x44E00500 /* Clock Module PLL Registers */
|
||||
|
||||
#define CLKSEL_TIMER1MS_CLK (CM_DPLL_BASE + 0x28)
|
||||
|
||||
|
||||
#define CLKSEL_TIMER1MS_CLK_SEL_MASK (0x7 << 0)
|
||||
#define CLKSEL_TIMER1MS_CLK_SEL_SEL1 (0x0 << 0) /* Select CLK_M_OSC clock */
|
||||
#define CLKSEL_TIMER1MS_CLK_SEL_SEL2 (0x1 << 0) /* Select CLK_32KHZ clock */
|
||||
#define CLKSEL_TIMER1MS_CLK_SEL_SEL3 (0x2 << 0) /* Select TCLKIN clock */
|
||||
#define CLKSEL_TIMER1MS_CLK_SEL_SEL4 (0x3 << 0) /* Select CLK_RC32K clock */
|
||||
#define CLKSEL_TIMER1MS_CLK_SEL_SEL5 (0x4 << 0) /* Selects the CLK_32768 from 32KHz Crystal Osc */
|
||||
|
||||
#define CLKSEL_TIMER7_CLK (CM_DPLL_BASE + 0x04)
|
||||
#define CLKSEL_TIMER7_CLK_SEL_MASK (0x3 << 0)
|
||||
#define CLKSEL_TIMER7_CLK_SEL_SEL1 (0x0 << 0) /* Select TCLKIN clock */
|
||||
#define CLKSEL_TIMER7_CLK_SEL_SEL2 (0x1 << 0) /* Select CLK_M_OSC clock */
|
||||
#define CLKSEL_TIMER7_CLK_SEL_SEL3 (0x2 << 0) /* Select CLK_32KHZ clock */
|
||||
#define CLKSEL_TIMER7_CLK_SEL_SEL4 (0x3 << 0) /* Reserved */
|
||||
|
||||
|
||||
|
||||
#endif /* AM335X */
|
||||
|
||||
#define OMAP3_CLKSEL_GPT1 (1 << 0) /* Selects GPTIMER 1 source
|
||||
* clock:
|
||||
|
|
|
|||
|
|
@ -11,7 +11,15 @@
|
|||
#include <sys/types.h>
|
||||
#include <assert.h>
|
||||
|
||||
#ifdef DM37XX
|
||||
//keesj:todo we don't want to hardcode these values here but ratter
|
||||
//get them using a system call. the same applies for the time offset
|
||||
static u64_t calib_hz = 1625000, Hz;
|
||||
#endif
|
||||
#ifdef AM335X
|
||||
static u64_t calib_hz = 1500000, Hz;
|
||||
#endif
|
||||
|
||||
#define MICROHZ 1000000ULL /* number of micros per second */
|
||||
#define MICROSPERTICK(h) (MICROHZ/(h)) /* number of micros per HZ tick */
|
||||
|
||||
|
|
@ -56,7 +64,12 @@ read_frclock(u32_t *frclk)
|
|||
volatile u32_t *frclock;
|
||||
|
||||
assert(frclk);
|
||||
frclock = (u32_t *)((u8_t *) _minix_kerninfo->minix_frclock+OMAP3_TCRR);
|
||||
#ifdef DM37XX
|
||||
frclock = (u32_t *)((u8_t *) _minix_kerninfo->minix_frclock + OMAP3_TIMER_TCRR);
|
||||
#endif
|
||||
#ifdef AM335X
|
||||
frclock = (u32_t *)((u8_t *) _minix_kerninfo->minix_frclock + AM335X_TIMER_TCRR);
|
||||
#endif
|
||||
*frclk = *frclock;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue