gem5/src
Gabe Black f2daf210f1 Initial changes to get O3 working with SPARC
src/arch/sparc/process.cc:
    MachineBytes doesn't exist any more.
src/arch/sparc/regfile.cc:
    Add in the miscRegFile for good measure.
src/cpu/o3/isa_specific.hh:
    Add in a section for SPARC
src/cpu/o3/sparc/cpu.cc:
src/cpu/o3/sparc/cpu.hh:
src/cpu/o3/sparc/cpu_builder.cc:
src/cpu/o3/sparc/cpu_impl.hh:
src/cpu/o3/sparc/dyn_inst.cc:
src/cpu/o3/sparc/dyn_inst.hh:
src/cpu/o3/sparc/dyn_inst_impl.hh:
src/cpu/o3/sparc/impl.hh:
src/cpu/o3/sparc/params.hh:
src/cpu/o3/sparc/thread_context.cc:
src/cpu/o3/sparc/thread_context.hh:
    Sparc version of this file.

--HG--
extra : convert_revision : 34bb5218f802d0a1328132a518cdd769fb59b6a4
2006-11-24 22:06:33 -05:00
..
arch Initial changes to get O3 working with SPARC 2006-11-24 22:06:33 -05:00
base add warn_once which will print any given warning message 2006-11-16 13:18:21 -08:00
cpu Initial changes to get O3 working with SPARC 2006-11-24 22:06:33 -05:00
dev Create a stub t1000 platform. 2006-11-14 15:14:27 -05:00
doxygen Fix up doxygen. 2006-08-14 19:25:07 -04:00
kern Moved the Alpha MiscRegFile into it's own file, and got rid of the Alpha specific DepTag constants. 2006-11-09 21:30:48 -05:00
mem Merge zizzer:/bk/newmem 2006-11-24 14:08:43 -05:00
python Added a parameter to set memory to zero. This is to support Legion, and once we can make our own hypervisor binary, we probably won't need it. 2006-11-22 23:09:27 -05:00
sim implement RUSAGE_CHILDREN for getrusage since it's trivial 2006-11-16 13:08:29 -08:00
unittest Merge iceaxe.:/Volumes/work/research/m5/head 2006-06-11 22:01:34 -04:00
Doxyfile Fix up doxygen. 2006-08-14 19:25:07 -04:00
SConscript Expose debugBreakCycle through swig and get rid of 2006-11-13 12:20:08 -08:00