Nilay Vaish 5c2fc35e02 O3 CPU LSQ: Implement TSO ... This patch makes O3's LSQ maintain total order between stores. Essentially only the store at the head of the store buffer is allowed to be in flight. Only after that store completes, the next store is issued to the memory system. By default, the x86 architecture will have TSO.		2012-01-28 19:09:04 -06:00
..
arch	MEM: Separate queries for snooping and address ranges	2012-01-17 12:55:09 -06:00
base	MEM: Add port proxies instead of non-structural ports	2012-01-17 12:55:08 -06:00
cpu	O3 CPU LSQ: Implement TSO	2012-01-28 19:09:04 -06:00
dev	ns_gige: Fix a missing curly brace in if-statement	2012-01-27 12:54:11 -05:00
doxygen	Fix up doxygen.	2006-08-14 19:25:07 -04:00
kern	MEM: Separate queries for snooping and address ranges	2012-01-17 12:55:09 -06:00
mem	Mem: Add simple bandwidth stats to PhysicalMemory	2012-01-25 17:18:25 +00:00
python	MEM: Removing the default port peer from Python ports	2012-01-17 12:55:09 -06:00
sim	sim: display final value of curTick in stats	2012-01-25 17:18:25 +00:00
unittest	Stats: Add a sparse histogram stat object.	2011-08-19 15:08:05 -05:00
Doxyfile	Fix up doxygen.	2006-08-14 19:25:07 -04:00
SConscript	SWIG: Make gem5 compile and link with swig 2.0.4	2012-01-09 18:08:20 -06:00