759ff4b910
build/SConstruct: Include Ozone CPU models. cpu/cpu_models.py: Include OzoneCPU models. --HG-- extra : convert_revision : 51a016c216cacd2cc613eed79653026c2edda4b3
242 lines
5.9 KiB
C++
242 lines
5.9 KiB
C++
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#ifndef __CPU_OZONE_FRONT_END_HH__
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#define __CPU_OZONE_FRONT_END_HH__
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#include <deque>
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//#include "cpu/ozone/cpu.hh"
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#include "cpu/inst_seq.hh"
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#include "cpu/o3/bpred_unit.hh"
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#include "cpu/ozone/rename_table.hh"
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//#include "cpu/ozone/thread_state.hh"
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#include "mem/mem_req.hh"
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#include "sim/eventq.hh"
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#include "sim/stats.hh"
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class ExecContext;
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class MemInterface;
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template <class>
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class OzoneThreadState;
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class PageTable;
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template <class>
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class TimeBuffer;
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template <class Impl>
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class FrontEnd
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{
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public:
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typedef typename Impl::Params Params;
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typedef typename Impl::DynInst DynInst;
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typedef typename Impl::DynInstPtr DynInstPtr;
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typedef typename Impl::FullCPU FullCPU;
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typedef typename Impl::BackEnd BackEnd;
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typedef typename Impl::FullCPU::OzoneXC OzoneXC;
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typedef typename Impl::FullCPU::CommStruct CommStruct;
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FrontEnd(Params *params);
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std::string name() const;
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void setCPU(FullCPU *cpu_ptr)
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{ cpu = cpu_ptr; }
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void setBackEnd(BackEnd *back_end_ptr)
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{ backEnd = back_end_ptr; }
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void setCommBuffer(TimeBuffer<CommStruct> *_comm);
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void setXC(ExecContext *xc_ptr);
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void setThreadState(OzoneThreadState<Impl> *thread_ptr)
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{ thread = thread_ptr; }
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void regStats();
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void tick();
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Fault fetchCacheLine();
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void processInst(DynInstPtr &inst);
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void squash(const InstSeqNum &squash_num, const Addr &next_PC,
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const bool is_branch = false, const bool branch_taken = false);
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DynInstPtr getInst();
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void processCacheCompletion();
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void addFreeRegs(int num_freed);
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bool isEmpty() { return instBuffer.empty(); }
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private:
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bool updateStatus();
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void checkBE();
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DynInstPtr getInstFromCacheline();
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void renameInst(DynInstPtr &inst);
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// Returns true if we need to stop the front end this cycle
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bool processBarriers(DynInstPtr &inst);
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void handleFault(Fault &fault);
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// Align an address (typically a PC) to the start of an I-cache block.
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// We fold in the PISA 64- to 32-bit conversion here as well.
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Addr icacheBlockAlignPC(Addr addr)
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{
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addr = TheISA::realPCToFetchPC(addr);
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return (addr & ~(cacheBlkMask));
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}
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InstSeqNum getAndIncrementInstSeq()
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{ return cpu->globalSeqNum++; }
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public:
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FullCPU *cpu;
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BackEnd *backEnd;
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ExecContext *xc;
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OzoneThreadState<Impl> *thread;
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enum Status {
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Running,
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Idle,
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IcacheMissStall,
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IcacheMissComplete,
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SerializeBlocked,
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SerializeComplete,
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RenameBlocked,
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BEBlocked
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};
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Status status;
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private:
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TimeBuffer<CommStruct> *comm;
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typename TimeBuffer<CommStruct>::wire fromCommit;
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typedef typename Impl::BranchPred BranchPred;
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// Typedef for semi-opaque type that holds any information the branch
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// predictor needs to update itself. Only two fields are used outside of
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// branch predictor, nextPC and isTaken.
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// typedef typename BranchPred::BPredInfo BPredInfo;
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BranchPred branchPred;
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class ICacheCompletionEvent : public Event
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{
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private:
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FrontEnd *frontEnd;
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public:
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ICacheCompletionEvent(FrontEnd *_fe);
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virtual void process();
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virtual const char *description();
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};
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ICacheCompletionEvent cacheCompletionEvent;
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MemInterface *icacheInterface;
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#if !FULL_SYSTEM
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PageTable *pTable;
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#endif
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MemReqPtr memReq;
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/** Mask to get a cache block's address. */
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Addr cacheBlkMask;
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unsigned cacheBlkSize;
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Addr cacheBlkPC;
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/** The cache line being fetched. */
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uint8_t *cacheData;
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bool fetchCacheLineNextCycle;
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bool cacheBlkValid;
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public:
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RenameTable<Impl> renameTable;
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private:
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Addr PC;
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Addr nextPC;
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public:
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void setPC(Addr val) { PC = val; }
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void setNextPC(Addr val) { nextPC = val; }
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void dumpInsts();
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private:
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typedef typename std::deque<DynInstPtr> InstBuff;
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typedef typename InstBuff::iterator InstBuffIt;
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InstBuff instBuffer;
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int instBufferSize;
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int maxInstBufferSize;
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int width;
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int freeRegs;
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int numPhysRegs;
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bool serializeNext;
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DynInstPtr barrierInst;
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// number of idle cycles
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/*
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Stats::Average<> notIdleFraction;
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Stats::Formula idleFraction;
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*/
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// @todo: Consider making these vectors and tracking on a per thread basis.
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/** Stat for total number of cycles stalled due to an icache miss. */
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Stats::Scalar<> icacheStallCycles;
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/** Stat for total number of fetched instructions. */
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Stats::Scalar<> fetchedInsts;
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Stats::Scalar<> fetchedBranches;
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/** Stat for total number of predicted branches. */
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Stats::Scalar<> predictedBranches;
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/** Stat for total number of cycles spent fetching. */
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Stats::Scalar<> fetchCycles;
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Stats::Scalar<> fetchIdleCycles;
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/** Stat for total number of cycles spent squashing. */
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Stats::Scalar<> fetchSquashCycles;
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/** Stat for total number of cycles spent blocked due to other stages in
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* the pipeline.
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*/
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Stats::Scalar<> fetchBlockedCycles;
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/** Stat for total number of fetched cache lines. */
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Stats::Scalar<> fetchedCacheLines;
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/** Distribution of number of instructions fetched each cycle. */
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Stats::Distribution<> fetchNisnDist;
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// Stats::Vector<> qfull_iq_occupancy;
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// Stats::VectorDistribution<> qfull_iq_occ_dist_;
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Stats::Formula idleRate;
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Stats::Formula branchRate;
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Stats::Formula fetchRate;
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Stats::Scalar<> IFQCount; // cumulative IFQ occupancy
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Stats::Formula IFQOccupancy;
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Stats::Formula IFQLatency;
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Stats::Scalar<> IFQFcount; // cumulative IFQ full count
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Stats::Formula IFQFullRate;
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Stats::Scalar<> dispatchCountStat;
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Stats::Scalar<> dispatchedSerializing;
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Stats::Scalar<> dispatchedTempSerializing;
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Stats::Scalar<> dispatchSerializeStallCycles;
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Stats::Formula dispatchRate;
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Stats::Formula regIntFull;
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Stats::Formula regFpFull;
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};
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#endif // __CPU_OZONE_FRONT_END_HH__
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