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gem5/src/arch/x86/insts
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Yasuko Eckert 2c293823aa cpu: add a condition-code register class 
Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
2013-10-15 14:22:44 -04:00
..
badmicroop.cc ISA: Put parser generated files in a "generated" directory. 2012-04-23 12:00:41 -07:00
badmicroop.hh StaticInst: Merge StaticInst and StaticInstBase. 2011-09-09 02:40:11 -07:00
macroop.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
microfpop.cc includes: sort all includes 2011-04-15 10:44:06 -07:00
microfpop.hh X86: Consolidate extra microop flags into one parameter. 2010-08-23 09:44:19 -07:00
microldstop.cc includes: sort all includes 2011-04-15 10:44:06 -07:00
microldstop.hh X86: Fix a tiny typo in the load/store microop constructor. 2012-04-15 01:07:39 -07:00
micromediaop.cc includes: sort all includes 2011-04-15 10:44:06 -07:00
micromediaop.hh X86: Consolidate extra microop flags into one parameter. 2010-08-23 09:44:19 -07:00
microop.cc X86: Create a directory for files that define register indexes. 2010-08-23 16:14:24 -07:00
microop.hh X86: Make sure instruction flags are set properly even on 32 bit machines. 2011-09-05 18:36:26 -07:00
microregop.cc trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
microregop.hh X86: Consolidate extra microop flags into one parameter. 2010-08-23 09:44:19 -07:00
static_inst.cc cpu: add a condition-code register class 2013-10-15 14:22:44 -04:00
static_inst.hh trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00