Nathan Binkert e99828b06a tick: rename Clock namespace to SimClock		2010-04-15 16:24:12 -07:00
..
cache	cache stats: account for writebacks and/or device occupancy in the cache.	2010-02-24 13:46:55 -08:00
config	Fixes to get prefetching working again.	2009-02-16 08:56:40 -08:00
gems_common	ruby: get rid of gems_common/util.hh and .cc and use stuff in src/base	2010-04-02 11:20:32 -07:00
protocol	ruby: get "using namespace" out of headers	2010-04-02 11:20:32 -07:00
ruby	ruby: get rid of gems_common/util.hh and .cc and use stuff in src/base	2010-04-02 11:20:32 -07:00
slicc	ruby: get rid of gems_common/util.hh and .cc and use stuff in src/base	2010-04-02 11:20:32 -07:00
bridge.cc	ruby: Added more info to bridge error message	2009-11-18 13:55:57 -08:00
bridge.hh	includes: use base/types.hh not inttypes.h or stdint.h	2009-05-17 14:34:51 -07:00
Bridge.py	DMA: Add IOCache and fix bus bridge to optionally only send requests one	2007-08-10 16:14:01 -04:00
bus.cc	bus: add assertion to catch illegal retry	2009-10-03 18:07:39 -07:00
bus.hh	types: clean up types, especially signed vs unsigned	2009-06-04 23:21:12 -07:00
Bus.py	python: Move more code into m5.util allow SCons to use that code.	2009-09-22 15:24:16 -07:00
dram.cc	style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs	2008-09-10 14:26:15 -04:00
dram.hh	stats: Fix all stats usages to deal with template fixes	2009-03-05 19:09:53 -08:00
mem_object.cc	params: Get rid of the remnants of the old style parameter configuration stuff.	2008-08-11 12:22:17 -07:00
mem_object.hh	params: Get rid of the remnants of the old style parameter configuration stuff.	2008-08-11 12:22:17 -07:00
MemObject.py	Major changes to how SimObjects are created and initialized. Almost all	2007-07-23 21:51:38 -07:00
mport.cc	X86: Add a function which gets called when an interrupt message has been delivered.	2009-04-19 03:54:11 -07:00
mport.hh	Create a message port for sending messages as apposed to reading/writing a memory range.	2008-10-12 12:08:51 -07:00
packet.cc	Memory: Rename LOCKED for load locked store conditional to LLSC.	2009-04-19 04:25:01 -07:00
packet.hh	packet: add a method to set the size	2010-03-12 17:31:08 -08:00
packet_access.hh	arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh	2009-09-23 08:34:21 -07:00
page_table.cc	util: do checkpoint aggregation more cleanly, fix last changeset.	2010-01-19 22:03:44 -08:00
page_table.hh	arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh	2009-09-23 08:34:21 -07:00
physical.cc	util: do checkpoint aggregation more cleanly, fix last changeset.	2010-01-19 22:03:44 -08:00
physical.hh	types: clean up types, especially signed vs unsigned	2009-06-04 23:21:12 -07:00
PhysicalMemory.py	Make default PhysicalMemory latency slightly more realistic.	2008-08-03 18:13:29 -04:00
port.cc	types: clean up types, especially signed vs unsigned	2009-06-04 23:21:12 -07:00
port.hh	types: clean up types, especially signed vs unsigned	2009-06-04 23:21:12 -07:00
port_impl.hh	arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh	2009-09-23 08:34:21 -07:00
request.hh	ruby: added the GEMS ruby tester	2010-01-29 20:29:23 -08:00
SConscript	ruby: Convert most Ruby objects to M5 SimObjects.	2010-01-29 20:29:17 -08:00
tport.cc	tick: rename Clock namespace to SimClock	2010-04-15 16:24:12 -07:00
tport.hh	Clean up the SimpleTimingPort class a little bit.	2008-11-10 11:51:18 -08:00
translating_port.cc	arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh	2009-09-23 08:34:21 -07:00
translating_port.hh	fix the translating ports so it can add a page on a fault	2007-05-09 15:37:46 -04:00
vport.cc	arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh	2009-09-23 08:34:21 -07:00
vport.hh	implement vtophys and 32bit gdb support	2007-02-18 19:57:46 -05:00