e0fdd86fd9
*** (1): get rid of expandForMT function MIPS is the only ISA that cares about having a piece of ISA state integrate multiple threads so add constants for MIPS and relieve the other ISAs from having to define this. Also, InOrder was the only core that was actively calling this function * * * (2): get rid of corespecific type The CoreSpecific type was used as a proxy to pass in HW specific params to a MIPS CPU, but since MIPS FS hasnt been touched for awhile, it makes sense to not force every other ISA to use CoreSpecific as well use a special reset function to set it. That probably should go in a PowerOn reset fault anyway.
202 lines
8.3 KiB
Python
202 lines
8.3 KiB
Python
# Copyright (c) 2005-2008 The Regents of The University of Michigan
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# Copyright (c) 2011 Regents of the University of California
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Nathan Binkert
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# Rick Strong
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import sys
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from m5.defines import buildEnv
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from m5.params import *
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from m5.proxy import *
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from Bus import Bus
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from InstTracer import InstTracer
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from ExeTracer import ExeTracer
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from MemObject import MemObject
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default_tracer = ExeTracer()
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if buildEnv['TARGET_ISA'] == 'alpha':
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from AlphaTLB import AlphaDTB, AlphaITB
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if buildEnv['FULL_SYSTEM']:
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from AlphaInterrupts import AlphaInterrupts
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elif buildEnv['TARGET_ISA'] == 'sparc':
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from SparcTLB import SparcTLB
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if buildEnv['FULL_SYSTEM']:
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from SparcInterrupts import SparcInterrupts
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elif buildEnv['TARGET_ISA'] == 'x86':
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from X86TLB import X86TLB
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if buildEnv['FULL_SYSTEM']:
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from X86LocalApic import X86LocalApic
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elif buildEnv['TARGET_ISA'] == 'mips':
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from MipsTLB import MipsTLB
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if buildEnv['FULL_SYSTEM']:
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from MipsInterrupts import MipsInterrupts
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elif buildEnv['TARGET_ISA'] == 'arm':
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from ArmTLB import ArmTLB
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if buildEnv['FULL_SYSTEM']:
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from ArmInterrupts import ArmInterrupts
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elif buildEnv['TARGET_ISA'] == 'power':
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from PowerTLB import PowerTLB
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if buildEnv['FULL_SYSTEM']:
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from PowerInterrupts import PowerInterrupts
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class BaseCPU(MemObject):
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type = 'BaseCPU'
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abstract = True
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system = Param.System(Parent.any, "system object")
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cpu_id = Param.Int(-1, "CPU identifier")
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numThreads = Param.Unsigned(1, "number of HW thread contexts")
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function_trace = Param.Bool(False, "Enable function trace")
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function_trace_start = Param.Tick(0, "Cycle to start function trace")
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checker = Param.BaseCPU(NULL, "checker CPU")
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do_checkpoint_insts = Param.Bool(True,
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"enable checkpoint pseudo instructions")
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do_statistics_insts = Param.Bool(True,
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"enable statistics pseudo instructions")
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if buildEnv['FULL_SYSTEM']:
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profile = Param.Latency('0ns', "trace the kernel stack")
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do_quiesce = Param.Bool(True, "enable quiesce instructions")
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else:
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workload = VectorParam.Process("processes to run")
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if buildEnv['TARGET_ISA'] == 'sparc':
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dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
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itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
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if buildEnv['FULL_SYSTEM']:
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interrupts = Param.SparcInterrupts(
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SparcInterrupts(), "Interrupt Controller")
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elif buildEnv['TARGET_ISA'] == 'alpha':
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dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
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itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
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if buildEnv['FULL_SYSTEM']:
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interrupts = Param.AlphaInterrupts(
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AlphaInterrupts(), "Interrupt Controller")
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elif buildEnv['TARGET_ISA'] == 'x86':
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dtb = Param.X86TLB(X86TLB(), "Data TLB")
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itb = Param.X86TLB(X86TLB(), "Instruction TLB")
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if buildEnv['FULL_SYSTEM']:
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_localApic = X86LocalApic(pio_addr=0x2000000000000000)
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interrupts = \
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Param.X86LocalApic(_localApic, "Interrupt Controller")
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elif buildEnv['TARGET_ISA'] == 'mips':
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dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
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itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
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if buildEnv['FULL_SYSTEM']:
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interrupts = Param.MipsInterrupts(
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MipsInterrupts(), "Interrupt Controller")
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elif buildEnv['TARGET_ISA'] == 'arm':
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dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
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itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
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if buildEnv['FULL_SYSTEM']:
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interrupts = Param.ArmInterrupts(
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ArmInterrupts(), "Interrupt Controller")
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elif buildEnv['TARGET_ISA'] == 'power':
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UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
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dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
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itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
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if buildEnv['FULL_SYSTEM']:
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interrupts = Param.PowerInterrupts(
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PowerInterrupts(), "Interrupt Controller")
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else:
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print "Don't know what TLB to use for ISA %s" % \
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buildEnv['TARGET_ISA']
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sys.exit(1)
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max_insts_all_threads = Param.Counter(0,
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"terminate when all threads have reached this inst count")
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max_insts_any_thread = Param.Counter(0,
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"terminate when any thread reaches this inst count")
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max_loads_all_threads = Param.Counter(0,
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"terminate when all threads have reached this load count")
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max_loads_any_thread = Param.Counter(0,
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"terminate when any thread reaches this load count")
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progress_interval = Param.Tick(0,
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"interval to print out the progress message")
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defer_registration = Param.Bool(False,
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"defer registration with system (for sampling)")
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clock = Param.Clock('1t', "clock speed")
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phase = Param.Latency('0ns', "clock phase")
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tracer = Param.InstTracer(default_tracer, "Instruction tracer")
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_cached_ports = []
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if buildEnv['TARGET_ISA'] in ['x86', 'arm'] and buildEnv['FULL_SYSTEM']:
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_cached_ports = ["itb.walker.port", "dtb.walker.port"]
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_uncached_ports = []
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if buildEnv['TARGET_ISA'] == 'x86' and buildEnv['FULL_SYSTEM']:
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_uncached_ports = ["interrupts.pio", "interrupts.int_port"]
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def connectCachedPorts(self, bus):
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for p in self._cached_ports:
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exec('self.%s = bus.port' % p)
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def connectUncachedPorts(self, bus):
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for p in self._uncached_ports:
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exec('self.%s = bus.port' % p)
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def connectAllPorts(self, cached_bus, uncached_bus = None):
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self.connectCachedPorts(cached_bus)
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if not uncached_bus:
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uncached_bus = cached_bus
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self.connectUncachedPorts(uncached_bus)
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def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
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assert(len(self._cached_ports) < 7)
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self.icache = ic
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self.dcache = dc
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self.icache_port = ic.cpu_side
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self.dcache_port = dc.cpu_side
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self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
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if buildEnv['FULL_SYSTEM']:
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if buildEnv['TARGET_ISA'] == 'x86':
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self.itb_walker_cache = iwc
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self.dtb_walker_cache = dwc
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self.itb.walker.port = iwc.cpu_side
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self.dtb.walker.port = dwc.cpu_side
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self._cached_ports += ["itb_walker_cache.mem_side", \
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"dtb_walker_cache.mem_side"]
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elif buildEnv['TARGET_ISA'] == 'arm':
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self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
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def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
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self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
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self.toL2Bus = Bus()
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self.connectCachedPorts(self.toL2Bus)
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self.l2cache = l2c
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self.l2cache.cpu_side = self.toL2Bus.port
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self._cached_ports = ['l2cache.mem_side']
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