ca0fd665dc
Names of DRAM configurations were updated to reflect both the channel and device data width. Previous naming format was: <DEVICE_TYPE>_<DATA_RATE>_<CHANNEL_WIDTH> The following nomenclature is now used: <DEVICE_TYPE>_<DATA_RATE>_<n>x<w> where n = The number of devices per rank on the channel x = Device width Total channel width can be calculated by n*w Example: A 64-bit DDR4, 2400 channel consisting of 4-bit devices: n = 16 w = 4 The resulting configuration name is: DDR4_2400_16x4 Updated scripts to match new naming convention. Added unique configurations for DDR4 for: 1) 16x4 2) 8x8 3) 4x16 Change-Id: Ibd7f763b7248835c624309143cb9fc29d56a69d1 Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> |
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.. | ||
__init__.py | ||
Benchmarks.py | ||
CacheConfig.py | ||
Caches.py | ||
cpu2000.py | ||
CpuConfig.py | ||
FSConfig.py | ||
GPUTLBConfig.py | ||
GPUTLBOptions.py | ||
HMC.py | ||
MemConfig.py | ||
O3_ARM_v7a.py | ||
Options.py | ||
PlatformConfig.py | ||
SimpleOpts.py | ||
Simulation.py | ||
SysPaths.py |