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mem: Update DRAM configuration names

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Names of DRAM configurations were updated to reflect both
the channel and device data width.

Previous naming format was:
	<DEVICE_TYPE>_<DATA_RATE>_<CHANNEL_WIDTH>

The following nomenclature is now used:
	<DEVICE_TYPE>_<DATA_RATE>_<n>x<w>
where n = The number of devices per rank on the channel
      x = Device width

Total channel width can be calculated by n*w

Example:
A 64-bit DDR4, 2400 channel consisting of 4-bit devices:
	n = 16
	w = 4
The resulting configuration name is:
	DDR4_2400_16x4

Updated scripts to match new naming convention.

Added unique configurations for DDR4 for:
1) 16x4
2) 8x8
3) 4x16

Change-Id: Ibd7f763b7248835c624309143cb9fc29d56a69d1
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
This commit is contained in:
Wendy Elsasser 2017-02-14 15:09:18 -06:00
parent 94e6126650
commit ca0fd665dc
47 changed files with 171 additions and 96 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
configs/common/HMC.py
View file

@ -58,7 +58,7 @@
# serial links, the main internal crossbar, and an external hmc controller.
#
# - VAULT CONTROLLERS:
# Instances of the HMC_2500_x32 class with their functionality specified in
# Instances of the HMC_2500_1x32 class with their functionality specified in
# dram_ctrl.cc
#
# - THE MAIN XBAR:

4
configs/common/MemConfig.py
View file

@ -152,7 +152,7 @@ def config_mem(options, system):
them.
"""
if ( options.mem_type == "HMC_2500_x32"):
if ( options.mem_type == "HMC_2500_1x32"):
HMChost = HMC.config_host_hmc(options, system)
HMC.config_hmc(options, system, HMChost.hmc_host)
subsystem = system.hmc_dev
@ -223,7 +223,7 @@ def config_mem(options, system):
# Connect the controllers to the membus
for i in xrange(len(subsystem.mem_ctrls)):
if (options.mem_type == "HMC_2500_x32"):
if (options.mem_type == "HMC_2500_1x32"):
subsystem.mem_ctrls[i].port = xbar[i/4].master
else:
subsystem.mem_ctrls[i].port = xbar.master

2
configs/common/Options.py
View file

@ -77,7 +77,7 @@ def addNoISAOptions(parser):
parser.add_option("--list-mem-types",
action="callback", callback=_listMemTypes,
help="List available memory types")
parser.add_option("--mem-type", type="choice", default="DDR3_1600_x64",
parser.add_option("--mem-type", type="choice", default="DDR3_1600_8x8",
choices=MemConfig.mem_names(),
help = "type of memory to use")
parser.add_option("--mem-channels", type="int", default=1,

2
configs/dram/lat_mem_rd.py
View file

@ -80,7 +80,7 @@ except:
parser = optparse.OptionParser()
parser.add_option("--mem-type", type="choice", default="DDR3_1600_x64",
parser.add_option("--mem-type", type="choice", default="DDR3_1600_8x8",
choices=MemConfig.mem_names(),
help = "type of memory to use")
parser.add_option("--mem-size", action="store", type="string",

4
configs/dram/sweep.py
View file

@ -53,8 +53,8 @@ from common import MemConfig
parser = optparse.OptionParser()
# Use a single-channel DDR3-1600 x64 by default
parser.add_option("--mem-type", type="choice", default="DDR3_1600_x64",
# Use a single-channel DDR3-1600 x64 (8x8 topology) by default
parser.add_option("--mem-type", type="choice", default="DDR3_1600_8x8",
choices=MemConfig.mem_names(),
help = "type of memory to use")

4
configs/example/hmctest.py
View file

@ -13,8 +13,8 @@ from common import HMC
parser = optparse.OptionParser()
# Use a HMC_2500_x32 by default
parser.add_option("--mem-type", type = "choice", default = "HMC_2500_x32",
# Use a HMC_2500_1x32 (1 channel, 32-bits wide) by default
parser.add_option("--mem-type", type = "choice", default = "HMC_2500_1x32",
choices = MemConfig.mem_names(),
help = "type of memory to use")

2
configs/example/memcheck.py
View file

@ -216,7 +216,7 @@ cfg_file.close()
proto_tester = TrafficGen(config_file = cfg_file_name)
# Set up the system along with a DRAM controller
system = System(physmem = DDR3_1600_x64())
system = System(physmem = DDR3_1600_8x8())
system.voltage_domain = VoltageDomain(voltage = '1V')

2
configs/learning_gem5/part1/simple.py
View file

@ -75,7 +75,7 @@ if m5.defines.buildEnv['TARGET_ISA'] == "x86":
system.cpu.interrupts[0].int_slave = system.membus.master
# Create a DDR3 memory controller and connect it to the membus
system.mem_ctrl = DDR3_1600_x64()
system.mem_ctrl = DDR3_1600_8x8()
system.mem_ctrl.range = system.mem_ranges[0]
system.mem_ctrl.port = system.membus.master

2
configs/learning_gem5/part1/two_level.py
View file

@ -128,7 +128,7 @@ if m5.defines.buildEnv['TARGET_ISA'] == "x86":
system.system_port = system.membus.slave
# Create a DDR3 memory controller
system.mem_ctrl = DDR3_1600_x64()
system.mem_ctrl = DDR3_1600_8x8()
system.mem_ctrl.range = system.mem_ranges[0]
system.mem_ctrl.port = system.membus.master

165
src/mem/DRAMCtrl.py
View file

@ -315,7 +315,7 @@ class DRAMCtrl(AbstractMemory):
# A single DDR3-1600 x64 channel (one command and address bus), with
# timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in
# an 8x8 configuration.
class DDR3_1600_x64(DRAMCtrl):
class DDR3_1600_8x8(DRAMCtrl):
# size of device in bytes
device_size = '512MB'
@ -410,7 +410,7 @@ class DDR3_1600_x64(DRAMCtrl):
# configuration.
# This configuration includes the latencies from the DRAM to the logic layer
# of the HMC
class HMC_2500_x32(DDR3_1600_x64):
class HMC_2500_1x32(DDR3_1600_8x8):
# size of device
# two banks per device with each bank 4MB [2]
device_size = '8MB'
@ -492,7 +492,7 @@ class HMC_2500_x32(DDR3_1600_x64):
# options for the DDR-1600 configuration, based on the same DDR3-1600
# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept
# consistent across the two configurations.
class DDR3_2133_x64(DDR3_1600_x64):
class DDR3_2133_8x8(DDR3_1600_8x8):
# 1066 MHz
tCK = '0.938ns'
@ -520,35 +520,37 @@ class DDR3_2133_x64(DDR3_1600_x64):
VDD = '1.5V'
# A single DDR4-2400 x64 channel (one command and address bus), with
# timings based on a DDR4-2400 4 Gbit datasheet (Micron MT40A512M16)
# in an 4x16 configuration.
class DDR4_2400_x64(DRAMCtrl):
# timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A2G4)
# in an 16x4 configuration.
# Total channel capacity is 32GB
# 16 devices/rank * 2 ranks/channel * 1GB/device = 32GB/channel
class DDR4_2400_16x4(DRAMCtrl):
# size of device
device_size = '512MB'
device_size = '1GB'
# 4x16 configuration, 4 devices each with an 16-bit interface
device_bus_width = 16
# 16x4 configuration, 16 devices each with a 4-bit interface
device_bus_width = 4
# DDR4 is a BL8 device
burst_length = 8
# Each device has a page (row buffer) size of 2 Kbyte (1K columns x16)
device_rowbuffer_size = '2kB'
# Each device has a page (row buffer) size of 512 byte (1K columns x4)
device_rowbuffer_size = '512B'
# 4x16 configuration, so 4 devices
devices_per_rank = 4
# 16x4 configuration, so 16 devices
devices_per_rank = 16
# Match our DDR3 configurations which is dual rank
ranks_per_channel = 2
# DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
# Set to 2 for x16 case
bank_groups_per_rank = 2
# Set to 4 for x4 case
bank_groups_per_rank = 4
# DDR4 has 16 banks(x4,x8) and 8 banks(x16) (4 bank groups in all
# configurations). Currently we do not capture the additional
# constraints incurred by the bank groups
banks_per_rank = 8
banks_per_rank = 16
# override the default buffer sizes and go for something larger to
# accommodate the larger bank count
@ -562,7 +564,7 @@ class DDR4_2400_x64(DRAMCtrl):
# tBURST is equivalent to the CAS-to-CAS delay (tCCD)
# With bank group architectures, tBURST represents the CAS-to-CAS
# delay for bursts to different bank groups (tCCD_S)
tBURST = '3.333ns'
tBURST = '3.332ns'
# @2400 data rate, tCCD_L is 6 CK
# CAS-to-CAS delay for bursts to the same bank group
@ -570,21 +572,23 @@ class DDR4_2400_x64(DRAMCtrl):
# for CAS-to-CAS delay for bursts to different bank groups
tCCD_L = '5ns';
# DDR4-2400 16-16-16
tRCD = '13.32ns'
tCL = '13.32ns'
tRP = '13.32ns'
tRAS = '35ns'
# DDR4-2400 17-17-17
tRCD = '14.16ns'
tCL = '14.16ns'
tRP = '14.16ns'
tRAS = '32ns'
# RRD_S (different bank group) for 2K page is MAX(4 CK, 5.3ns)
tRRD = '5.3ns'
# RRD_S (different bank group) for 512B page is MAX(4 CK, 3.3ns)
tRRD = '3.332ns'
# RRD_L (same bank group) for 2K page is MAX(4 CK, 6.4ns)
tRRD_L = '6.4ns';
# RRD_L (same bank group) for 512B page is MAX(4 CK, 4.9ns)
tRRD_L = '4.9ns';
tXAW = '30ns'
# tFAW for 512B page is MAX(16 CK, 13ns)
tXAW = '13.328ns'
activation_limit = 4
tRFC = '260ns'
# tRFC is 350ns
tRFC = '350ns'
tWR = '15ns'
@ -607,27 +611,98 @@ class DDR4_2400_x64(DRAMCtrl):
tXP = '6ns'
# self refresh exit time
tXS = '120ns'
# exit delay to ACT, PRE, PREALL, REF, SREF Enter, and PD Enter is:
# tRFC + 10ns = 340ns
tXS = '340ns'
# Current values from datasheet
IDD0 = '70mA'
IDD02 = '4.6mA'
IDD2N = '50mA'
IDD3N = '67mA'
IDD0 = '43mA'
IDD02 = '3mA'
IDD2N = '34mA'
IDD3N = '38mA'
IDD3N2 = '3mA'
IDD4W = '302mA'
IDD4R = '230mA'
IDD5 = '192mA'
IDD3P1 = '44mA'
IDD2P1 = '32mA'
IDD6 = '20mA'
IDD4W = '103mA'
IDD4R = '110mA'
IDD5 = '250mA'
IDD3P1 = '32mA'
IDD2P1 = '25mA'
IDD6 = '30mA'
VDD = '1.2V'
VDD2 = '2.5V'
# A single DDR4-2400 x64 channel (one command and address bus), with
# timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A1G8)
# in an 8x8 configuration.
# Total channel capacity is 16GB
# 8 devices/rank * 2 ranks/channel * 1GB/device = 16GB/channel
class DDR4_2400_8x8(DDR4_2400_16x4):
# 8x8 configuration, 8 devices each with an 8-bit interface
device_bus_width = 8
# Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
device_rowbuffer_size = '1kB'
# RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns)
tRRD_L = '4.9ns';
tXAW = '21ns'
# Current values from datasheet
IDD0 = '48mA'
IDD3N = '43mA'
IDD4W = '123mA'
IDD4R = '135mA'
IDD3P1 = '37mA'
# A single DDR4-2400 x64 channel (one command and address bus), with
# timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A512M16)
# in an 4x16 configuration.
# Total channel capacity is 4GB
# 4 devices/rank * 1 ranks/channel * 1GB/device = 4GB/channel
class DDR4_2400_4x16(DDR4_2400_16x4):
# 4x16 configuration, 4 devices each with an 16-bit interface
device_bus_width = 16
# Each device has a page (row buffer) size of 2 Kbyte (1K columns x16)
device_rowbuffer_size = '2kB'
# 4x16 configuration, so 4 devices
devices_per_rank = 4
# Single rank for x16
ranks_per_channel = 1
# DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
# Set to 2 for x16 case
bank_groups_per_rank = 2
# DDR4 has 16 banks(x4,x8) and 8 banks(x16) (4 bank groups in all
# configurations). Currently we do not capture the additional
# constraints incurred by the bank groups
banks_per_rank = 8
# RRD_S (different bank group) for 2K page is MAX(4 CK, 5.3ns)
tRRD = '5.3ns'
# RRD_L (same bank group) for 2K page is MAX(4 CK, 6.4ns)
tRRD_L = '6.4ns';
tXAW = '30ns'
# Current values from datasheet
IDD0 = '80mA'
IDD02 = '4mA'
IDD2N = '34mA'
IDD3N = '47mA'
IDD4W = '228mA'
IDD4R = '243mA'
IDD5 = '280mA'
IDD3P1 = '41mA'
# A single LPDDR2-S4 x32 interface (one command/address bus), with
# default timings based on a LPDDR2-1066 4 Gbit part (Micron MT42L128M32D1)
# in a 1x32 configuration.
class LPDDR2_S4_1066_x32(DRAMCtrl):
class LPDDR2_S4_1066_1x32(DRAMCtrl):
# No DLL in LPDDR2
dll = False
@ -726,7 +801,7 @@ class LPDDR2_S4_1066_x32(DRAMCtrl):
# A single WideIO x128 interface (one command and address bus), with
# default timings based on an estimated WIO-200 8 Gbit part.
class WideIO_200_x128(DRAMCtrl):
class WideIO_200_1x128(DRAMCtrl):
# No DLL for WideIO
dll = False
@ -795,7 +870,7 @@ class WideIO_200_x128(DRAMCtrl):
# A single LPDDR3 x32 interface (one command/address bus), with
# default timings based on a LPDDR3-1600 4 Gbit part (Micron
# EDF8132A1MC) in a 1x32 configuration.
class LPDDR3_1600_x32(DRAMCtrl):
class LPDDR3_1600_1x32(DRAMCtrl):
# No DLL for LPDDR3
dll = False
@ -895,7 +970,7 @@ class LPDDR3_1600_x32(DRAMCtrl):
# A single GDDR5 x64 interface, with
# default timings based on a GDDR5-4000 1 Gbit part (SK Hynix
# H5GQ1H24AFR) in a 2x32 configuration.
class GDDR5_4000_x64(DRAMCtrl):
class GDDR5_4000_2x32(DRAMCtrl):
# size of device
device_size = '128MB'
@ -979,7 +1054,7 @@ class GDDR5_4000_x64(DRAMCtrl):
# IDD measurement values, and by extrapolating data from other classes.
# Architecture values based on published HBM spec
# A 4H stack is defined, 2Gb per die for a total of 1GB of memory.
class HBM_1000_4H_x128(DRAMCtrl):
class HBM_1000_4H_1x128(DRAMCtrl):
# HBM gen1 supports up to 8 128-bit physical channels
# Configuration defines a single channel, with the capacity
# set to (full_ stack_capacity / 8) based on 2Gb dies
@ -1068,7 +1143,7 @@ class HBM_1000_4H_x128(DRAMCtrl):
# instantiated per pseudo-channel
# Stay at same IO rate (1Gbps) to maintain timing relationship with
# HBM gen1 class (HBM_1000_4H_x128) where possible
class HBM_1000_4H_x64(HBM_1000_4H_x128):
class HBM_1000_4H_1x64(HBM_1000_4H_1x128):
# For HBM gen2 with pseudo-channel mode, configure 2X channels.
# Configuration defines a single pseudo channel, with the capacity
# set to (full_ stack_capacity / 16) based on 8Gb dies

2
tests/configs/minor-timing-mp.py
View file

@ -42,5 +42,5 @@ from m5.objects import *
from base_config import *
nb_cores = 4
root = BaseSESystem(mem_mode='timing', mem_class=DDR3_1600_x64,
root = BaseSESystem(mem_mode='timing', mem_class=DDR3_1600_8x8,
cpu_class=MinorCPU, num_cpus=nb_cores).create_root()

2
tests/configs/minor-timing.py
View file

@ -41,5 +41,5 @@
from m5.objects import *
from base_config import *
root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_8x8,
cpu_class=MinorCPU).create_root()

2
tests/configs/o3-timing-checker.py
View file

@ -38,6 +38,6 @@
from m5.objects import *
from base_config import *
root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_8x8,
cpu_class=DerivO3CPU,
checker=True).create_root()

2
tests/configs/o3-timing-mp.py
View file

@ -42,5 +42,5 @@ from m5.objects import *
from base_config import *
nb_cores = 4
root = BaseSESystem(mem_mode='timing', mem_class=DDR3_1600_x64,
root = BaseSESystem(mem_mode='timing', mem_class=DDR3_1600_8x8,
cpu_class=DerivO3CPU, num_cpus=nb_cores).create_root()

4
tests/configs/o3-timing-mt.py
View file

@ -48,10 +48,10 @@ from common.O3_ARM_v7a import O3_ARM_v7a_3
# configuration. This makes the results more meaningful, and also
# increases the coverage of the regressions.
if buildEnv['TARGET_ISA'] == "arm":
root = ArmSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
root = ArmSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_8x8,
cpu_class=O3_ARM_v7a_3,
num_threads=2).create_root()
else:
root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_8x8,
cpu_class=DerivO3CPU,
num_threads=2).create_root()

4
tests/configs/o3-timing.py
View file

@ -48,8 +48,8 @@ from common.O3_ARM_v7a import O3_ARM_v7a_3
# configuration. This makes the results more meaningful, and also
# increases the coverage of the regressions.
if buildEnv['TARGET_ISA'] == "arm":
root = ArmSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
root = ArmSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_8x8,
cpu_class=O3_ARM_v7a_3).create_root()
else:
root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_8x8,
cpu_class=DerivO3CPU).create_root()

2
tests/configs/pc-o3-timing.py
View file

@ -39,5 +39,5 @@ from m5.objects import *
from x86_generic import *
root = LinuxX86FSSystemUniprocessor(mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=DerivO3CPU).create_root()

2
tests/configs/pc-simple-timing.py
View file

@ -39,6 +39,6 @@ from m5.objects import *
from x86_generic import *
root = LinuxX86FSSystemUniprocessor(mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=TimingSimpleCPU).create_root()

2
tests/configs/pc-switcheroo-full.py
View file

@ -42,7 +42,7 @@ from x86_generic import *
import switcheroo
root = LinuxX86FSSwitcheroo(
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_classes=(AtomicSimpleCPU, TimingSimpleCPU, DerivO3CPU)
).create_root()

2
tests/configs/realview-minor-dual.py
View file

@ -39,6 +39,6 @@ from m5.objects import *
from arm_generic import *
root = LinuxArmFSSystem(mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=MinorCPU,
num_cpus=2).create_root()

2
tests/configs/realview-minor.py
View file

@ -39,5 +39,5 @@ from m5.objects import *
from arm_generic import *
root = LinuxArmFSSystemUniprocessor(mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=MinorCPU).create_root()

2
tests/configs/realview-o3-checker.py
View file

@ -40,6 +40,6 @@ from arm_generic import *
from common.O3_ARM_v7a import O3_ARM_v7a_3
root = LinuxArmFSSystemUniprocessor(mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=O3_ARM_v7a_3,
checker=True).create_root()

2
tests/configs/realview-o3-dual.py
View file

@ -40,6 +40,6 @@ from arm_generic import *
from common.O3_ARM_v7a import O3_ARM_v7a_3
root = LinuxArmFSSystem(mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=O3_ARM_v7a_3,
num_cpus=2).create_root()

2
tests/configs/realview-o3.py
View file

@ -40,5 +40,5 @@ from arm_generic import *
from common.O3_ARM_v7a import O3_ARM_v7a_3
root = LinuxArmFSSystemUniprocessor(mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=O3_ARM_v7a_3).create_root()

2
tests/configs/realview-simple-timing-dual.py
View file

@ -39,6 +39,6 @@ from m5.objects import *
from arm_generic import *
root = LinuxArmFSSystem(mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=TimingSimpleCPU,
num_cpus=2).create_root()

2
tests/configs/realview-simple-timing.py
View file

@ -39,5 +39,5 @@ from m5.objects import *
from arm_generic import *
root = LinuxArmFSSystemUniprocessor(mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=TimingSimpleCPU).create_root()

2
tests/configs/realview-switcheroo-full.py
View file

@ -40,7 +40,7 @@ from arm_generic import *
import switcheroo
root = LinuxArmFSSwitcheroo(
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_classes=(AtomicSimpleCPU, TimingSimpleCPU, MinorCPU, DerivO3CPU)
).create_root()

2
tests/configs/realview-switcheroo-o3.py
View file

@ -40,7 +40,7 @@ from arm_generic import *
import switcheroo
root = LinuxArmFSSwitcheroo(
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_classes=(DerivO3CPU, DerivO3CPU)
).create_root()

2
tests/configs/realview-switcheroo-timing.py
View file

@ -40,7 +40,7 @@ from arm_generic import *
import switcheroo
root = LinuxArmFSSwitcheroo(
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_classes=(TimingSimpleCPU, TimingSimpleCPU)
).create_root()

2
tests/configs/realview64-minor-dual.py
View file

@ -40,6 +40,6 @@ from arm_generic import *
root = LinuxArmFSSystem(machine_type='VExpress_EMM64',
mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=MinorCPU,
num_cpus=2).create_root()

2
tests/configs/realview64-minor.py
View file

@ -40,5 +40,5 @@ from arm_generic import *
root = LinuxArmFSSystemUniprocessor(machine_type='VExpress_EMM64',
mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=MinorCPU).create_root()

2
tests/configs/realview64-o3-checker.py
View file

@ -41,6 +41,6 @@ from common.O3_ARM_v7a import O3_ARM_v7a_3
root = LinuxArmFSSystemUniprocessor(machine_type='VExpress_EMM64',
mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=O3_ARM_v7a_3,
checker=True).create_root()

2
tests/configs/realview64-o3-dual.py
View file

@ -41,6 +41,6 @@ from common.O3_ARM_v7a import O3_ARM_v7a_3
root = LinuxArmFSSystem(machine_type='VExpress_EMM64',
mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=O3_ARM_v7a_3,
num_cpus=2).create_root()

2
tests/configs/realview64-o3.py
View file

@ -41,5 +41,5 @@ from common.O3_ARM_v7a import O3_ARM_v7a_3
root = LinuxArmFSSystemUniprocessor(machine_type='VExpress_EMM64',
mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=O3_ARM_v7a_3).create_root()

2
tests/configs/realview64-simple-timing-dual.py
View file

@ -40,6 +40,6 @@ from arm_generic import *
root = LinuxArmFSSystem(machine_type='VExpress_EMM64',
mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=TimingSimpleCPU,
num_cpus=2).create_root()

2
tests/configs/realview64-simple-timing.py
View file

@ -40,5 +40,5 @@ from arm_generic import *
root = LinuxArmFSSystemUniprocessor(machine_type='VExpress_EMM64',
mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=TimingSimpleCPU).create_root()

2
tests/configs/realview64-switcheroo-full.py
View file

@ -41,7 +41,7 @@ import switcheroo
root = LinuxArmFSSwitcheroo(
machine_type='VExpress_EMM64',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_classes=(AtomicSimpleCPU, TimingSimpleCPU, MinorCPU, DerivO3CPU)
).create_root()

2
tests/configs/realview64-switcheroo-o3.py
View file

@ -41,7 +41,7 @@ import switcheroo
root = LinuxArmFSSwitcheroo(
machine_type='VExpress_EMM64',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_classes=(DerivO3CPU, DerivO3CPU)
).create_root()

2
tests/configs/realview64-switcheroo-timing.py
View file

@ -41,7 +41,7 @@ import switcheroo
root = LinuxArmFSSwitcheroo(
machine_type='VExpress_EMM64',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_classes=(TimingSimpleCPU, TimingSimpleCPU)
).create_root()

2
tests/configs/tgen-dram-ctrl.py
View file

@ -49,7 +49,7 @@ cpu = TrafficGen(
config_file=srcpath("tests/quick/se/70.tgen/tgen-dram-ctrl.cfg"))
# system simulated
system = System(cpu = cpu, physmem = DDR3_1600_x64(),
system = System(cpu = cpu, physmem = DDR3_1600_8x8(),
membus = IOXBar(width = 16),
clk_domain = SrcClockDomain(clock = '1GHz',
voltage_domain =

2
tests/configs/tsunami-minor-dual.py
View file

@ -39,6 +39,6 @@ from m5.objects import *
from alpha_generic import *
root = LinuxAlphaFSSystem(mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=MinorCPU,
num_cpus=2).create_root()

2
tests/configs/tsunami-minor.py
View file

@ -39,5 +39,5 @@ from m5.objects import *
from alpha_generic import *
root = LinuxAlphaFSSystemUniprocessor(mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=MinorCPU).create_root()

2
tests/configs/tsunami-o3-dual.py
View file

@ -39,6 +39,6 @@ from m5.objects import *
from alpha_generic import *
root = LinuxAlphaFSSystem(mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=DerivO3CPU,
num_cpus=2).create_root()

2
tests/configs/tsunami-o3.py
View file

@ -39,5 +39,5 @@ from m5.objects import *
from alpha_generic import *
root = LinuxAlphaFSSystemUniprocessor(mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=DerivO3CPU).create_root()

2
tests/configs/tsunami-simple-timing-dual.py
View file

@ -39,6 +39,6 @@ from m5.objects import *
from alpha_generic import *
root = LinuxAlphaFSSystem(mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=TimingSimpleCPU,
num_cpus=2).create_root()

2
tests/configs/tsunami-simple-timing.py
View file

@ -39,5 +39,5 @@ from m5.objects import *
from alpha_generic import *
root = LinuxAlphaFSSystemUniprocessor(mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=TimingSimpleCPU).create_root()

2
tests/configs/tsunami-switcheroo-full.py
View file

@ -40,7 +40,7 @@ from alpha_generic import *
import switcheroo
root = LinuxAlphaFSSwitcheroo(
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_classes=(AtomicSimpleCPU, TimingSimpleCPU, DerivO3CPU)
).create_root()