config: Add configs scripts used in Learning gem5
Added a new directory in configs (learning_gem5) to hold the scripts that are used in the book. See http://lowepower.com/jason/learning_gem5/ for a working copy. For now, only the scripts in Part 1: Getting started with gem5 have been added. A separate patch adds tests for these scripts. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
This commit is contained in:
Jason Lowe-Power
parent
0d6a6dfd7b
commit
f065f9941b
73
configs/common/SimpleOpts.py
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73
configs/common/SimpleOpts.py
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# -*- coding: utf-8 -*-
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# Copyright (c) 2015 Jason Power
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Jason Power
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""" Options wrapper for simple gem5 configuration scripts
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This module wraps the optparse class so that we can register options
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from each class instead of only from the configuration script.
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"""
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# Module-level variable to track if we've called the parse_args function yet
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called_parse_args = False
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# For fatal
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import m5
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# import the options parser
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from optparse import OptionParser
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# add the options we want to be able to control from the command line
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parser = OptionParser()
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def add_option(*args, **kwargs):
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"""Call "add_option" to the global options parser
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"""
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if (parser.has_option(args[0]) or
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(len(args) > 1 and parser.has_option(args[1])) ):
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m5.fatal("Duplicate option: %s" % str(args))
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if called_parse_args:
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m5.fatal("Can't add an option after calling SimpleOpts.parse_args")
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parser.add_option(*args, **kwargs)
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def parse_args():
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global called_parse_args
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called_parse_args = True
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return parser.parse_args()
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def set_usage(*args, **kwargs):
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parser.set_usage(*args, **kwargs)
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def print_help(*args, **kwargs):
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parser.print_help(*args, **kwargs)
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29
configs/learning_gem5/README
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29
configs/learning_gem5/README
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Learning_gem README
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-------------------
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This directory contains the configuration scripts used in the "Learning gem5"
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book. The scripts contained in these directories are for educational purposes
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only and should not be used for architectural research as-is.
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"Learning gem5" is currently in early development stages. A pre-alpha working
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version of the book can be found at the following URL.
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http://lowepower.com/jason/learning_gem5/
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This directory is broken into one subdirectory per part of the book.
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Goals of these scripts
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~~~~~~~~~~~~~~~~~~~~~~
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These scripts are not necessarily useful outside the scope of the learning
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gem5 book. The goal is to include the learning gem5 scripts, following the
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book as closely as possible, so that the regression tester will catch any
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changes that affect the book.
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For general users, these are *not* good scripts to use for running complex
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architectural experiments. These scripts *are* a good starting point example
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of how to write your own scripts for experiments.
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Feedback
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~~~~~~~~
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Send mail to power.jg@gmail.com to provide feedback.
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127
configs/learning_gem5/part1/caches.py
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127
configs/learning_gem5/part1/caches.py
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# -*- coding: utf-8 -*-
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# Copyright (c) 2015 Jason Power
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
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# documentation and/or other materials provided with the distribution;
|
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# neither the name of the copyright holders nor the names of its
|
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# contributors may be used to endorse or promote products derived from
|
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# this software without specific prior written permission.
|
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#
|
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Jason Power
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""" Caches with options for a simple gem5 configuration script
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This file contains L1 I/D and L2 caches to be used in the simple
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gem5 configuration script. It uses the SimpleOpts wrapper to set up command
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line options from each individual class.
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"""
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from m5.objects import Cache
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import SimpleOpts
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# Some specific options for caches
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# For all options see src/mem/cache/BaseCache.py
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class L1Cache(Cache):
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"""Simple L1 Cache with default values"""
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assoc = 2
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hit_latency = 2
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response_latency = 2
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mshrs = 4
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tgts_per_mshr = 20
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def __init__(self, options=None):
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super(L1Cache, self).__init__()
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pass
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def connectBus(self, bus):
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"""Connect this cache to a memory-side bus"""
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self.mem_side = bus.slave
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def connectCPU(self, cpu):
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"""Connect this cache's port to a CPU-side port
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This must be defined in a subclass"""
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raise NotImplementedError
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class L1ICache(L1Cache):
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"""Simple L1 instruction cache with default values"""
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# Set the default size
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size = '16kB'
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SimpleOpts.add_option('--l1i_size',
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help="L1 instruction cache size. Default: %s" % size)
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def __init__(self, opts=None):
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super(L1ICache, self).__init__(opts)
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if not opts or not opts.l1i_size:
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return
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self.size = opts.l1i_size
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def connectCPU(self, cpu):
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"""Connect this cache's port to a CPU icache port"""
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self.cpu_side = cpu.icache_port
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class L1DCache(L1Cache):
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"""Simple L1 data cache with default values"""
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# Set the default size
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size = '64kB'
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SimpleOpts.add_option('--l1d_size',
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help="L1 data cache size. Default: %s" % size)
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def __init__(self, opts=None):
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super(L1DCache, self).__init__(opts)
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if not opts or not opts.l1d_size:
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return
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self.size = opts.l1d_size
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def connectCPU(self, cpu):
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"""Connect this cache's port to a CPU dcache port"""
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self.cpu_side = cpu.dcache_port
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class L2Cache(Cache):
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"""Simple L2 Cache with default values"""
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# Default parameters
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size = '256kB'
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assoc = 8
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hit_latency = 20
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response_latency = 20
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mshrs = 20
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tgts_per_mshr = 12
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SimpleOpts.add_option('--l2_size', help="L2 cache size. Default: %s" % size)
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def __init__(self, opts=None):
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super(L2Cache, self).__init__()
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if not opts or not opts.l2_size:
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return
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self.size = opts.l2_size
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def connectCPUSideBus(self, bus):
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self.cpu_side = bus.master
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def connectMemSideBus(self, bus):
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self.mem_side = bus.slave
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107
configs/learning_gem5/part1/simple.py
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107
configs/learning_gem5/part1/simple.py
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@ -0,0 +1,107 @@
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# -*- coding: utf-8 -*-
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# Copyright (c) 2015 Jason Power
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
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# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
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# contributors may be used to endorse or promote products derived from
|
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# this software without specific prior written permission.
|
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Jason Power
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""" This file creates a barebones system and executes 'hello', a simple Hello
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World application.
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See Part 1, Chapter 2: Creating a simple configuration script in the
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learning_gem5 book for more information about this script.
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IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
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also needs to be updated. For now, email Jason <power.jg@gmail.com>
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"""
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# import the m5 (gem5) library created when gem5 is built
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import m5
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# import all of the SimObjects
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from m5.objects import *
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# create the system we are going to simulate
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system = System()
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# Set the clock fequency of the system (and all of its children)
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system.clk_domain = SrcClockDomain()
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system.clk_domain.clock = '1GHz'
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system.clk_domain.voltage_domain = VoltageDomain()
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# Set up the system
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system.mem_mode = 'timing' # Use timing accesses
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system.mem_ranges = [AddrRange('512MB')] # Create an address range
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# Create a simple CPU
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system.cpu = TimingSimpleCPU()
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# Create a memory bus, a system crossbar, in this case
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system.membus = SystemXBar()
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# Hook the CPU ports up to the membus
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system.cpu.icache_port = system.membus.slave
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system.cpu.dcache_port = system.membus.slave
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# create the interrupt controller for the CPU and connect to the membus
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system.cpu.createInterruptController()
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# For x86 only, make sure the interrupts are connected to the memory
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# Note: these are directly connected to the memory bus and are not cached
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if m5.defines.buildEnv['TARGET_ISA'] == "x86":
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system.cpu.interrupts.pio = system.membus.master
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system.cpu.interrupts.int_master = system.membus.slave
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system.cpu.interrupts.int_slave = system.membus.master
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# Create a DDR3 memory controller and connect it to the membus
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system.mem_ctrl = DDR3_1600_x64()
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system.mem_ctrl.range = system.mem_ranges[0]
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system.mem_ctrl.port = system.membus.master
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# Connect the system up to the membus
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system.system_port = system.membus.slave
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# get ISA for the binary to run.
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isa = str(m5.defines.buildEnv['TARGET_ISA']).lower()
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# Run 'hello' and use the compiled ISA to find the binary
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binary = 'tests/test-progs/hello/bin/' + isa + '/linux/hello'
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# Create a process for a simple "Hello World" application
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process = LiveProcess()
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# Set the command
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# cmd is a list which begins with the executable (like argv)
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process.cmd = [binary]
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# Set the cpu to use the process as its workload and create thread contexts
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system.cpu.workload = process
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system.cpu.createThreads()
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# set up the root SimObject and start the simulation
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root = Root(full_system = False, system = system)
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# instantiate all of the objects we've created above
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m5.instantiate()
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print "Beginning simulation!"
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exit_event = m5.simulate()
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print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause())
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151
configs/learning_gem5/part1/two_level.py
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151
configs/learning_gem5/part1/two_level.py
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# -*- coding: utf-8 -*-
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# Copyright (c) 2015 Jason Power
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Jason Power
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""" This file creates a single CPU and a two-level cache system.
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This script takes a single parameter which specifies a binary to execute.
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If none is provided it executes 'hello' by default (mostly used for testing)
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See Part 1, Chapter 3: Adding cache to the configuration script in the
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learning_gem5 book for more information about this script.
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This file exports options for the L1 I/D and L2 cache sizes.
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IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
|
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also needs to be updated. For now, email Jason <power.jg@gmail.com>
|
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"""
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# import the m5 (gem5) library created when gem5 is built
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import m5
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# import all of the SimObjects
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from m5.objects import *
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# Add the common scripts to our path
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m5.util.addToPath('../../common')
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# import the caches which we made
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from caches import *
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# import the SimpleOpts module
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import SimpleOpts
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# Set the usage message to display
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SimpleOpts.set_usage("usage: %prog [options] <binary to execute>")
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# Finalize the arguments and grab the opts so we can pass it on to our objects
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(opts, args) = SimpleOpts.parse_args()
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# get ISA for the default binary to run. This is mostly for simple testing
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isa = str(m5.defines.buildEnv['TARGET_ISA']).lower()
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# Default to running 'hello', use the compiled ISA to find the binary
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binary = 'tests/test-progs/hello/bin/' + isa + '/linux/hello'
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# Check if there was a binary passed in via the command line and error if
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# there are too many arguments
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if len(args) == 1:
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binary = args[0]
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elif len(args) > 1:
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SimpleOpts.print_help()
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m5.fatal("Expected a binary to execute as positional argument")
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# create the system we are going to simulate
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system = System()
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# Set the clock fequency of the system (and all of its children)
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system.clk_domain = SrcClockDomain()
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system.clk_domain.clock = '1GHz'
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system.clk_domain.voltage_domain = VoltageDomain()
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# Set up the system
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system.mem_mode = 'timing' # Use timing accesses
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system.mem_ranges = [AddrRange('512MB')] # Create an address range
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# Create a simple CPU
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system.cpu = TimingSimpleCPU()
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# Create an L1 instruction and data cache
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system.cpu.icache = L1ICache(opts)
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system.cpu.dcache = L1DCache(opts)
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# Connect the instruction and data caches to the CPU
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system.cpu.icache.connectCPU(system.cpu)
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system.cpu.dcache.connectCPU(system.cpu)
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# Create a memory bus, a coherent crossbar, in this case
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system.l2bus = L2XBar()
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# Hook the CPU ports up to the l2bus
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system.cpu.icache.connectBus(system.l2bus)
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system.cpu.dcache.connectBus(system.l2bus)
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# Create an L2 cache and connect it to the l2bus
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system.l2cache = L2Cache(opts)
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system.l2cache.connectCPUSideBus(system.l2bus)
|
||||
|
||||
# Create a memory bus
|
||||
system.membus = SystemXBar()
|
||||
|
||||
# Connect the L2 cache to the membus
|
||||
system.l2cache.connectMemSideBus(system.membus)
|
||||
|
||||
# create the interrupt controller for the CPU
|
||||
system.cpu.createInterruptController()
|
||||
|
||||
# For x86 only, make sure the interrupts are connected to the memory
|
||||
# Note: these are directly connected to the memory bus and are not cached
|
||||
if m5.defines.buildEnv['TARGET_ISA'] == "x86":
|
||||
system.cpu.interrupts.pio = system.membus.master
|
||||
system.cpu.interrupts.int_master = system.membus.slave
|
||||
system.cpu.interrupts.int_slave = system.membus.master
|
||||
|
||||
# Connect the system up to the membus
|
||||
system.system_port = system.membus.slave
|
||||
|
||||
# Create a DDR3 memory controller
|
||||
system.mem_ctrl = DDR3_1600_x64()
|
||||
system.mem_ctrl.range = system.mem_ranges[0]
|
||||
system.mem_ctrl.port = system.membus.master
|
||||
|
||||
# Create a process for a simple "Hello World" application
|
||||
process = LiveProcess()
|
||||
# Set the command
|
||||
# cmd is a list which begins with the executable (like argv)
|
||||
process.cmd = [binary]
|
||||
# Set the cpu to use the process as its workload and create thread contexts
|
||||
system.cpu.workload = process
|
||||
system.cpu.createThreads()
|
||||
|
||||
# set up the root SimObject and start the simulation
|
||||
root = Root(full_system = False, system = system)
|
||||
# instantiate all of the objects we've created above
|
||||
m5.instantiate()
|
||||
|
||||
print "Beginning simulation!"
|
||||
exit_event = m5.simulate()
|
||||
print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause())
|
||||
Loading…
Reference in a new issue