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gem5/src/cpu
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Steve Reinhardt 89cf3f6e85 Move sched_list.hh and timebuf.hh from src/base to src/cpu. 
These files really aren't general enough to belong in src/base.
This patch doesn't reorder include lines, leaving them unsorted
in many cases, but Nate's magic script will fix that up shortly.

--HG--
rename : src/base/sched_list.hh => src/cpu/sched_list.hh
rename : src/base/timebuf.hh => src/cpu/timebuf.hh
2011-01-03 14:35:47 -08:00
..
checker ARM/Alpha/Cpu: Change prefetchs to be more like normal loads. 2010-11-08 13:58:22 -06:00
inorder Move sched_list.hh and timebuf.hh from src/base to src/cpu. 2011-01-03 14:35:47 -08:00
nocpu SCons: Support building without an ISA 2010-11-19 18:00:39 -06:00
o3 Move sched_list.hh and timebuf.hh from src/base to src/cpu. 2011-01-03 14:35:47 -08:00
ozone Move sched_list.hh and timebuf.hh from src/base to src/cpu. 2011-01-03 14:35:47 -08:00
pred ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. 2010-10-31 00:07:20 -07:00
simple O3: Make all instructions that write a misc. register not perform the write until commit. 2010-12-07 16:19:57 -08:00
testers This patch removes the WARN_* and ERROR_* from src/mem/ruby/common/Debug.hh file. These statements have been replaced with warn(), panic() and fatal() defined in src/base/misc.hh 2010-12-22 23:15:24 -06:00
trace request: rename INST_READ to INST_FETCH. 2009-04-20 18:54:02 -07:00
activity.cc Move sched_list.hh and timebuf.hh from src/base to src/cpu. 2011-01-03 14:35:47 -08:00
activity.hh Move sched_list.hh and timebuf.hh from src/base to src/cpu. 2011-01-03 14:35:47 -08:00
base.cc ARM: Support switchover with hardware table walkers 2010-12-07 16:19:57 -08:00
base.hh O3: Make O3 support variably lengthed instructions. 2010-11-15 19:37:03 -08:00
base_dyn_inst.hh O3: Support squashing all state after special instruction 2010-12-07 16:19:57 -08:00
base_dyn_inst_impl.hh ARM/Alpha/Cpu: Change prefetchs to be more like normal loads. 2010-11-08 13:58:22 -06:00
BaseCPU.py X86: Loosen an assert for x86 and connect the APIC ports when caches are used. 2010-11-23 06:11:50 -05:00
CheckerCPU.py python: Move more code into m5.util allow SCons to use that code. 2009-09-22 15:24:16 -07:00
cpuevent.cc Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh. 2006-06-06 17:32:21 -04:00
cpuevent.hh eventq: convert all usage of events to use the new API. 2008-10-09 04:58:24 -07:00
exec_context.hh ARM/Alpha/Cpu: Change prefetchs to be more like normal loads. 2010-11-08 13:58:22 -06:00
exetrace.cc Make commenting on close namespace brackets consistent. 2011-01-03 14:35:43 -08:00
exetrace.hh Make commenting on close namespace brackets consistent. 2011-01-03 14:35:43 -08:00
ExeTracer.py SimObjects: Clean up handling of C++ namespaces. 2008-10-09 22:19:39 -07:00
func_unit.cc params: Deprecate old-style constructors; update most SimObject constructors. 2007-08-30 15:16:59 -04:00
func_unit.hh params: Deprecate old-style constructors; update most SimObject constructors. 2007-08-30 15:16:59 -04:00
FuncUnit.py CPU/ARM: Add SIMD op classes to CPU models and ARM ISA. 2010-11-15 14:04:04 -06:00
inst_seq.hh build: fix compile problems pointed out by gcc 4.4 2009-11-04 16:57:01 -08:00
inteltrace.cc Make commenting on close namespace brackets consistent. 2011-01-03 14:35:43 -08:00
inteltrace.hh Make commenting on close namespace brackets consistent. 2011-01-03 14:35:43 -08:00
IntelTrace.py SimObjects: Clean up handling of C++ namespaces. 2008-10-09 22:19:39 -07:00
intr_control.cc style: Use the correct m5 style for things relating to interrupts. 2008-10-21 07:12:53 -07:00
intr_control.hh Interrupts: Inline some code and remove duplication. 2007-11-08 10:46:41 -05:00
IntrControl.py Move SimObject python files alongside the C++ and fix 2007-05-27 19:21:17 -07:00
legiontrace.cc Make commenting on close namespace brackets consistent. 2011-01-03 14:35:43 -08:00
legiontrace.hh Make commenting on close namespace brackets consistent. 2011-01-03 14:35:43 -08:00
LegionTrace.py SimObjects: Clean up handling of C++ namespaces. 2008-10-09 22:19:39 -07:00
m5legion_interface.h add fsr to the list of registers we are interested in 2007-01-30 18:27:04 -05:00
nativetrace.cc Make commenting on close namespace brackets consistent. 2011-01-03 14:35:43 -08:00
nativetrace.hh Make commenting on close namespace brackets consistent. 2011-01-03 14:35:43 -08:00
NativeTrace.py ARM: Make native trace print out what instruction caused an error. 2009-07-27 00:54:09 -07:00
op_class.hh CPU/ARM: Add SIMD op classes to CPU models and ARM ISA. 2010-11-15 14:04:04 -06:00
pc_event.cc ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. 2010-10-31 00:07:20 -07:00
pc_event.hh types: Move stuff for global types into src/base/types.hh 2009-05-17 14:34:50 -07:00
profile.cc Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh. 2006-06-06 17:32:21 -04:00
profile.hh arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh 2009-09-23 08:34:21 -07:00
quiesce_event.cc eventq: convert all usage of events to use the new API. 2008-10-09 04:58:24 -07:00
quiesce_event.hh Make the Event::description() a const function 2008-02-06 16:32:40 -05:00
sched_list.hh Move sched_list.hh and timebuf.hh from src/base to src/cpu. 2011-01-03 14:35:47 -08:00
SConscript SCons: Support building without an ISA 2010-11-19 18:00:39 -06:00
simple_thread.cc sim: Use forward declarations for ports. 2010-11-08 13:58:22 -06:00
simple_thread.hh ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. 2010-10-31 00:07:20 -07:00
smt.hh types: add a type for thread IDs and try to use it everywhere 2009-05-26 09:23:13 -07:00
static_inst.cc ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. 2010-10-31 00:07:20 -07:00
static_inst.hh O3: Support squashing all state after special instruction 2010-12-07 16:19:57 -08:00
thread_context.cc ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. 2010-10-31 00:07:20 -07:00
thread_context.hh ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. 2010-10-31 00:07:20 -07:00
thread_state.cc CPU: Get rid of the now unnecessary getInst/setInst family of functions. 2010-09-13 21:58:34 -07:00
thread_state.hh CPU: Get rid of the now unnecessary getInst/setInst family of functions. 2010-09-13 21:58:34 -07:00
timebuf.hh Move sched_list.hh and timebuf.hh from src/base to src/cpu. 2011-01-03 14:35:47 -08:00
translation.hh Faults: Pass the StaticInst involved, if any, to a Fault's invoke method. 2010-09-13 19:26:03 -07:00