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Andreas Hansson d64b34bef8 arm: Share a port for the two table walker objects This patch changes how the MMU and table walkers are created such that a single port is used to connect the MMU and the TLBs to the memory system. Previously two ports were needed as there are two table walker objects (stage one and stage two), and they both had a port. Now the port itself is moved to the Stage2MMU, and each TableWalker is simply using the port from the parent. By using the same port we also remove the need for having an additional crossbar joining the two ports before the walker cache or the L2. This simplifies the creation of the CPU cache topology in BaseCPU.py considerably. Moreover, for naming and symmetry reasons, the TLB walker port is connected through the stage-one table walker thus making the naming identical to x86. Along the same line, we use the stage-one table walker to generate the master id that is used by all TLB-related requests.		2015-03-02 04:00:42 -05:00
build_opts	scons: Do not build the InOrderCPU	2015-01-20 08:12:45 -05:00
configs	Ruby: Update backing store option to propagate through to all RubyPorts	2015-02-26 09:58:26 -06:00
ext	ext: Bump DRAMPower to avoid compilation issues	2014-10-20 18:03:53 -04:00
src	arm: Share a port for the two table walker objects	2015-03-02 04:00:42 -05:00
system	arm: Add support for ARMv8 (AArch64 & AArch32)	2014-01-24 15:29:34 -06:00
tests	tests: Run regression timeout as foreground	2015-03-02 04:00:29 -05:00
util	cpu: add support for outputing a protobuf formatted CPU trace	2015-02-16 03:32:38 -05:00
.hgignore	ext: Add a McPAT regression tester	2014-06-04 07:48:20 -07:00
.hgtags	Added tag stable_2014_12_14 for changeset bdb307e8be54	2014-12-14 16:21:04 -06:00
COPYING	copyright: Add code for finding all copyright blocks and create a COPYING file	2011-06-02 17:36:07 -07:00
LICENSE	copyright: Add code for finding all copyright blocks and create a COPYING file	2011-06-02 17:36:07 -07:00
README	misc: README direct to website for dependencies	2014-08-26 10:12:04 -04:00
SConstruct	tests: Run regression timeout as foreground	2015-03-02 04:00:29 -05:00

README

This is the gem5 simulator.

The main website can be found at http://www.gem5.org

A good starting point is http://www.gem5.org/Introduction, and for
more information about building the simulator and getting started
please see http://www.gem5.org/Documentation and
http://www.gem5.org/Tutorials.

To build gem5, you will need the following software: g++ or clang,
Python (gem5 links in the Python interpreter), SCons, SWIG, zlib, m4,
and lastly protobuf if you want trace capture and playback
support. Please see http://www.gem5.org/Dependencies for more details
concerning the minimum versions of the aforementioned tools.

Once you have all dependencies resolved, type 'scons
build/<ARCH>/gem5.opt' where ARCH is one of ALPHA, ARM, NULL, MIPS,
POWER, SPARC, or X86. This will build an optimized version of the gem5
binary (gem5.opt) for the the specified architecture. See
http://www.gem5.org/Build_System for more details and options.

With the simulator built, have a look at
http://www.gem5.org/Running_gem5 for more information on how to use
gem5.

The basic source release includes these subdirectories:
   - configs: example simulation configuration scripts
   - ext: less-common external packages needed to build gem5
   - src: source code of the gem5 simulator
   - system: source for some optional system software for simulated systems
   - tests: regression tests
   - util: useful utility programs and files

To run full-system simulations, you will need compiled system firmware
(console and PALcode for Alpha), kernel binaries and one or more disk
images. Please see the gem5 download page for these items at
http://www.gem5.org/Download

If you have questions, please send mail to gem5-users@gem5.org

Enjoy using gem5 and please share your modifications and extensions.