gem5/src/cpu/inorder
Korey Sewell d64226750e inorder: remove request map, use request vector
take away all instances of reqMap in the code and make all references use the built-in
request vectors inside of each resource. The request map was dynamically allocating
a request per instruction. The request vector just allocates N number of requests
during instantiation and then the surrounding code is fixed up to reuse those N requests
***
setRequest() and clearRequest() are the new accessors needed to define a new
request in a resource
2011-02-18 14:28:30 -05:00
..
resources inorder: remove request map, use request vector 2011-02-18 14:28:30 -05:00
comm.hh inorder: stage width as a python parameter 2011-02-04 00:08:18 -05:00
cpu.cc inorder: remove request map, use request vector 2011-02-18 14:28:30 -05:00
cpu.hh inorder: remove reqRemoveList 2011-02-18 14:28:10 -05:00
first_stage.cc inorder: utilize cached skeds in pipeline 2011-02-12 10:14:45 -05:00
first_stage.hh inorder: pipe. stage inst. buffering 2011-02-04 00:08:16 -05:00
inorder_cpu_builder.cc inorder-alpha-fs: edit inorder model to compile FS mode 2009-09-15 01:44:48 -04:00
inorder_dyn_inst.cc inorder: clean up the old way of inst. scheduling 2011-02-12 10:14:48 -05:00
inorder_dyn_inst.hh inorder: clean up the old way of inst. scheduling 2011-02-12 10:14:48 -05:00
inorder_trace.cc Make commenting on close namespace brackets consistent. 2011-01-03 14:35:43 -08:00
inorder_trace.hh Make commenting on close namespace brackets consistent. 2011-01-03 14:35:43 -08:00
InOrderCPU.py inorder: add a fetch buffer to fetch unit 2011-02-04 00:08:22 -05:00
InOrderTrace.py InOrder: Import new inorder CPU model from MIPS. 2009-02-10 15:49:29 -08:00
params.hh Remove unused functions/comments cluttering up the code. 2009-03-04 13:17:08 -05:00
pipeline_stage.cc inorder: remove request map, use request vector 2011-02-18 14:28:30 -05:00
pipeline_stage.hh inorder: pipe. stage inst. buffering 2011-02-04 00:08:16 -05:00
pipeline_traits.5stage.cc InOrder: Import new inorder CPU model from MIPS. 2009-02-10 15:49:29 -08:00
pipeline_traits.5stage.hh InOrder: Import new inorder CPU model from MIPS. 2009-02-10 15:49:29 -08:00
pipeline_traits.9stage.cc InOrder: Import new inorder CPU model from MIPS. 2009-02-10 15:49:29 -08:00
pipeline_traits.9stage.hh InOrder: Import new inorder CPU model from MIPS. 2009-02-10 15:49:29 -08:00
pipeline_traits.9stage.smt2.cc InOrder: Import new inorder CPU model from MIPS. 2009-02-10 15:49:29 -08:00
pipeline_traits.9stage.smt2.hh InOrder: Import new inorder CPU model from MIPS. 2009-02-10 15:49:29 -08:00
pipeline_traits.hh inorder: clean up the old way of inst. scheduling 2011-02-12 10:14:48 -05:00
reg_dep_map.cc Replace curTick global variable with accessor functions. 2011-01-07 21:50:29 -08:00
reg_dep_map.hh inorder: enforce 78-character rule 2010-06-24 15:34:12 -04:00
resource.cc inorder: remove request map, use request vector 2011-02-18 14:28:30 -05:00
resource.hh inorder: remove request map, use request vector 2011-02-18 14:28:30 -05:00
resource_pool.9stage.cc Replace curTick global variable with accessor functions. 2011-01-07 21:50:29 -08:00
resource_pool.cc inorder: utilize cached skeds in pipeline 2011-02-12 10:14:45 -05:00
resource_pool.hh inorder: utilize cached skeds in pipeline 2011-02-12 10:14:45 -05:00
resource_sked.cc inorder: utilize cached skeds in pipeline 2011-02-12 10:14:45 -05:00
resource_sked.hh inorder: define iterator for resource schedules 2011-02-12 10:14:43 -05:00
SConscript inorder: clean up the old way of inst. scheduling 2011-02-12 10:14:48 -05:00
SConsopts cpu_models: get rid of cpu_models.py and move the stuff into SCons 2010-02-26 18:14:48 -08:00
thread_context.cc ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. 2010-10-31 00:07:20 -07:00
thread_context.hh ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. 2010-10-31 00:07:20 -07:00
thread_state.cc inorder-alpha-fs: edit inorder model to compile FS mode 2009-09-15 01:44:48 -04:00
thread_state.hh ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. 2010-10-31 00:07:20 -07:00