d53c6c168a
Mostly a matter of keeping prefetches to invalid addrs
from messing up VM IPRs. Also discovered that wh64s were
not being treated as prefetches, when they really should be
(for the most part, anyway).
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
- Get rid of intrlock flag for locking VM fault regs (a la EV5);
instead, just don't update regs on VPTE loads (a la EV6).
- Add NO_FAULT MemReq flag to indicate references that should not
cause page faults (i.e., prefetches).
arch/alpha/ev5.cc:
- Get rid of intrlock flag for locking VM fault regs (a la EV5);
instead, just don't update regs on VPTE loads (a la EV6).
- Add Fault trace flag.
arch/alpha/isa_desc:
- Add NO_FAULT MemReq flag to indicate references that should not
cause page faults (i.e., prefetches).
- Mark wh64 as a "data prefetch" instruction so it gets controlled
properly by the FullCPU data prefetch control switch.
- Align wh64 EA in decoder so issue stage doesn't need to worry about it.
arch/alpha/isa_traits.hh:
- Get rid of intrlock flag for locking VM fault regs (a la EV5);
instead, just don't update regs on VPTE loads (a la EV6).
base/traceflags.py:
- Add Fault trace flag.
cpu/simple_cpu/simple_cpu.hh:
- Pass MemReq flags to writeHint() operation.
cpu/static_inst.hh:
Update comment re: prefetches.
--HG--
extra : convert_revision : 62e466b0f4c0ff9961796270fa2e371ec24bcbb6
125 lines
4 KiB
C++
125 lines
4 KiB
C++
/*
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* Copyright (c) 2003 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ALPHA_MEMORY_HH__
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#define __ALPHA_MEMORY_HH__
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#include <map>
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#include "mem/mem_req.hh"
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#include "sim/sim_object.hh"
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#include "base/statistics.hh"
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class ExecContext;
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class AlphaTLB : public SimObject
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{
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protected:
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typedef std::multimap<Addr, int> PageTable;
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PageTable lookupTable; // Quick lookup into page table
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AlphaISA::PTE *table; // the Page Table
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int size; // TLB Size
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int nlu; // not last used entry (for replacement)
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void nextnlu() { if (++nlu >= size) nlu = 0; }
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AlphaISA::PTE *lookup(Addr vpn, uint8_t asn) const;
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public:
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AlphaTLB(const std::string &name, int size);
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virtual ~AlphaTLB();
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int getsize() const { return size; }
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AlphaISA::PTE &index(bool advance = true);
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void insert(Addr vaddr, AlphaISA::PTE &pte);
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void flushAll();
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void flushProcesses();
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void flushAddr(Addr addr, uint8_t asn);
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// static helper functions... really EV5 VM traits
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static bool validVirtualAddress(Addr vaddr) {
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// unimplemented bits must be all 0 or all 1
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Addr unimplBits = vaddr & VA_UNIMPL_MASK;
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return (unimplBits == 0) || (unimplBits == VA_UNIMPL_MASK);
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}
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static void checkCacheability(MemReqPtr &req);
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// Checkpointing
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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};
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class AlphaITB : public AlphaTLB
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{
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protected:
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mutable Stats::Scalar<> hits;
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mutable Stats::Scalar<> misses;
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mutable Stats::Scalar<> acv;
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mutable Stats::Formula accesses;
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protected:
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void fault(Addr pc, ExecContext *xc) const;
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public:
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AlphaITB(const std::string &name, int size);
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virtual void regStats();
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Fault translate(MemReqPtr &req) const;
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};
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class AlphaDTB : public AlphaTLB
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{
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protected:
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mutable Stats::Scalar<> read_hits;
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mutable Stats::Scalar<> read_misses;
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mutable Stats::Scalar<> read_acv;
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mutable Stats::Scalar<> read_accesses;
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mutable Stats::Scalar<> write_hits;
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mutable Stats::Scalar<> write_misses;
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mutable Stats::Scalar<> write_acv;
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mutable Stats::Scalar<> write_accesses;
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Stats::Formula hits;
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Stats::Formula misses;
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Stats::Formula acv;
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Stats::Formula accesses;
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protected:
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void fault(MemReqPtr &req, uint64_t flags) const;
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public:
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AlphaDTB(const std::string &name, int size);
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virtual void regStats();
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Fault translate(MemReqPtr &req, bool write) const;
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};
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#endif // __ALPHA_MEMORY_HH__
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