Ron Dreslinski cd0b65508e Make an initialization pass for the thread context and set the [phys,virt]Port correctly ... src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: Call the thread context initialization --HG-- extra : convert_revision : d7dc2a8b893dc670077b7f6150d4b710a1778620		2006-11-17 21:55:28 -05:00
..
arch	interrupts.hh:	2006-11-14 12:59:57 -05:00
base	set TRACING_ON one way or another explicitly in the	2006-11-11 20:46:56 -08:00
cpu	Make an initialization pass for the thread context and set the [phys,virt]Port correctly	2006-11-17 21:55:28 -05:00
dev	fix endian issues with condition codes	2006-11-10 20:17:42 -05:00
doxygen	Fix up doxygen.	2006-08-14 19:25:07 -04:00
kern	Moved the Alpha MiscRegFile into it's own file, and got rid of the Alpha specific DepTag constants.	2006-11-09 21:30:48 -05:00
mem	Fix bugs around uni-coherence invalidates being propogated properly.	2006-11-14 17:15:05 -05:00
python	Update phase param in the .py file for the cpus	2006-11-14 01:13:26 -05:00
sim	Expose debugBreakCycle through swig and get rid of	2006-11-13 12:20:08 -08:00
unittest	Merge iceaxe.:/Volumes/work/research/m5/head	2006-06-11 22:01:34 -04:00
Doxyfile	Fix up doxygen.	2006-08-14 19:25:07 -04:00
SConscript	Expose debugBreakCycle through swig and get rid of	2006-11-13 12:20:08 -08:00