gem5/src/arch/arm/isa
2010-06-02 12:58:07 -05:00
..
decoder ARM: Decode 32 bit thumb data processing register instructions. 2010-06-02 12:58:06 -05:00
formats ARM: Decode the sign/zero extend instructions. 2010-06-02 12:58:07 -05:00
insts ARM: Implement zero/sign extend instructions. 2010-06-02 12:58:07 -05:00
templates ARM: Add a base class for extend and add instructions. 2010-06-02 12:58:07 -05:00
bitfields.isa ARM: Hook the new multiply instructions into all the decoders. 2010-06-02 12:58:03 -05:00
copyright.txt ARM: Remove IsControl from operands that don't imply control transfers. 2010-06-02 12:57:59 -05:00
includes.isa ARM: Define versions of MSR and MRS outside the decoder. 2010-06-02 12:58:05 -05:00
main.isa ARM: Define the load instructions from outside the decoder. 2010-06-02 12:58:01 -05:00
operands.isa ARM: Make LDM that loads the PC perform an interworking branch. 2010-06-02 12:58:05 -05:00