.. |
AbstractReplacementPolicy.hh
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ruby: replace Time with Tick in replacement policy classes
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2013-02-10 21:43:08 -06:00 |
BankedArray.cc
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ruby banked array: do away with event scheduling
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2012-10-15 17:27:15 -05:00 |
BankedArray.hh
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ruby banked array: do away with event scheduling
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2012-10-15 17:27:15 -05:00 |
Cache.py
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ruby: replaces Time with Cycles in many places
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2013-02-10 21:26:24 -06:00 |
CacheMemory.cc
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Ruby: Remove RubyEventQueue
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2012-08-27 01:00:55 -05:00 |
CacheMemory.hh
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scons: Add warning for missing declarations
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2013-02-19 05:56:07 -05:00 |
DirectoryMemory.cc
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Ruby: remove config information from ruby.stats
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2012-07-12 08:39:19 -05:00 |
DirectoryMemory.hh
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Ruby: remove config information from ruby.stats
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2012-07-12 08:39:19 -05:00 |
DirectoryMemory.py
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sim: Include object header files in SWIG interfaces
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2012-11-02 11:32:01 -05:00 |
DMASequencer.cc
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ruby: enable multiple clock domains
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2013-02-10 21:43:17 -06:00 |
DMASequencer.hh
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scons: Fix warnings issued by clang 3.2svn (XCode 4.6)
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2013-02-19 05:56:08 -05:00 |
LRUPolicy.hh
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ruby: replace Time with Tick in replacement policy classes
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2013-02-10 21:43:08 -06:00 |
MachineID.hh
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Ruby: Fix compilation errors on gcc 4.7 and clang 3.2
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2013-02-14 12:24:51 -05:00 |
MemoryControl.cc
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ruby: improved support for functional accesses
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2012-10-15 17:51:57 -05:00 |
MemoryControl.hh
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ruby: replace Time with Cycles in Memory Controller
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2013-02-10 21:26:25 -06:00 |
MemoryControl.py
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sim: Include object header files in SWIG interfaces
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2012-11-02 11:32:01 -05:00 |
MemoryNode.cc
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ruby: style pass
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2010-03-22 18:43:53 -07:00 |
MemoryNode.hh
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ruby: replace Time with Cycles in Memory Controller
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2013-02-10 21:26:25 -06:00 |
MemoryVector.hh
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Ruby: Use uint32_t instead of uint32 everywhere
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2012-09-11 09:24:45 -05:00 |
PerfectCacheMemory.hh
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Ruby: remove config information from ruby.stats
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2012-07-12 08:39:19 -05:00 |
PersistentTable.cc
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ruby: get rid of the Map class
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2010-06-10 23:17:07 -07:00 |
PersistentTable.hh
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Ruby: remove config information from ruby.stats
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2012-07-12 08:39:19 -05:00 |
PseudoLRUPolicy.hh
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ruby: replace Time with Tick in replacement policy classes
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2013-02-10 21:43:08 -06:00 |
RubyMemoryControl.cc
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sim: Make clock private and access using clockPeriod()
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2013-02-19 05:56:06 -05:00 |
RubyMemoryControl.hh
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scons: Add warning for missing declarations
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2013-02-19 05:56:07 -05:00 |
RubyMemoryControl.py
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ruby: replaces Time with Cycles in many places
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2013-02-10 21:26:24 -06:00 |
RubyPort.cc
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scons: Fix warnings issued by clang 3.2svn (XCode 4.6)
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2013-02-19 05:56:08 -05:00 |
RubyPort.hh
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scons: Fix warnings issued by clang 3.2svn (XCode 4.6)
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2013-02-19 05:56:08 -05:00 |
RubyPortProxy.cc
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MEM: Add port proxies instead of non-structural ports
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2012-01-17 12:55:08 -06:00 |
RubyPortProxy.hh
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MEM: Add port proxies instead of non-structural ports
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2012-01-17 12:55:08 -06:00 |
RubySystem.py
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ruby: convert block size, memory size to unsigned
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2013-02-10 21:43:07 -06:00 |
SConscript
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ruby: banked cache array resource model
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2012-07-10 22:51:54 -07:00 |
Sequencer.cc
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ruby: mesi coherence protocol: invalidate lock
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2013-02-28 10:04:26 -06:00 |
Sequencer.hh
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ruby: mesi coherence protocol: invalidate lock
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2013-02-28 10:04:26 -06:00 |
Sequencer.py
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ruby: remove the functional copy of memory in se mode
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2013-03-06 21:53:57 -06:00 |
SparseMemory.cc
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Ruby Sparse Memory: Add function for collating blocks
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2012-01-11 13:29:54 -06:00 |
SparseMemory.hh
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Ruby: remove config information from ruby.stats
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2012-07-12 08:39:19 -05:00 |
System.cc
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ruby: fixes functional writes to RubyRequest
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2013-03-02 23:12:55 -06:00 |
System.hh
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ruby: enable multiple clock domains
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2013-02-10 21:43:17 -06:00 |
TBETable.hh
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ruby: replace Time with Cycles (final patch in the series)
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2013-02-10 21:43:10 -06:00 |
TimerTable.cc
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ruby: replace Time with Cycles (final patch in the series)
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2013-02-10 21:43:10 -06:00 |
TimerTable.hh
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ruby: replace Time with Cycles (final patch in the series)
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2013-02-10 21:43:10 -06:00 |
WireBuffer.cc
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ruby: enable multiple clock domains
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2013-02-10 21:43:17 -06:00 |
WireBuffer.hh
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scons: Add warning for missing declarations
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2013-02-19 05:56:07 -05:00 |
WireBuffer.py
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sim: Include object header files in SWIG interfaces
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2012-11-02 11:32:01 -05:00 |