Kevin Lim a8b03e4d01 Updates for O3 model. ... arch/alpha/isa/decoder.isa: Make IPR accessing instructions serializing so they are not issued incorrectly in the O3 model. arch/alpha/isa/pal.isa: Allow IPR instructions to have flags. base/traceflags.py: Include new trace flags from the two new CPU models. cpu/SConscript: Create the templates for the split mem accessor methods. Also include the new files from the new models (the Ozone model will be checked in next). cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: Update to the BaseDynInst for the new models. --HG-- extra : convert_revision : cc82db9c72ec3e29cea4c3fdff74a3843e287a35		2006-04-22 18:26:48 -04:00
..
alpha	Updates for O3 model.	2006-04-22 18:26:48 -04:00
mips	last changes before big merge	2006-03-09 03:27:51 -05:00
sparc	fix merging issues	2006-03-09 16:17:10 -05:00
isa_parser.py	Changes to support automatic renaming of the shadow registers at decode time. This requires using an ExtMachInst (uint64_t) instead of the normal MachInst; the ExtMachInst is packed with extra decode context information. In the case of Alpha, the PAL mode is included.	2006-03-03 15:28:25 -05:00
isa_specific.hh	Auto-generate arch/foo.hh "switch headers" in scons.	2006-02-22 22:22:06 -05:00
SConscript	Pushed ev5.hh out of the non-alpha code.	2006-03-07 14:08:01 -05:00