972 lines
30 KiB
Text
972 lines
30 KiB
Text
|
|
================ Begin RubySystem Configuration Print ================
|
|
|
|
RubySystem config:
|
|
random_seed: 1234
|
|
randomization: 1
|
|
cycle_period: 1
|
|
block_size_bytes: 64
|
|
block_size_bits: 6
|
|
memory_size_bytes: 134217728
|
|
memory_size_bits: 27
|
|
|
|
Network Configuration
|
|
---------------------
|
|
network: SIMPLE_NETWORK
|
|
topology:
|
|
|
|
virtual_net_0: active, ordered
|
|
virtual_net_1: active, ordered
|
|
virtual_net_2: active, unordered
|
|
virtual_net_3: active, unordered
|
|
virtual_net_4: active, unordered
|
|
virtual_net_5: active, unordered
|
|
virtual_net_6: inactive
|
|
virtual_net_7: inactive
|
|
virtual_net_8: inactive
|
|
virtual_net_9: inactive
|
|
|
|
|
|
Profiler Configuration
|
|
----------------------
|
|
periodic_stats_period: 1000000
|
|
|
|
================ End RubySystem Configuration Print ================
|
|
|
|
|
|
Real time: Jan/10/2012 12:44:12
|
|
|
|
Profiler Stats
|
|
--------------
|
|
Elapsed_time_in_seconds: 0
|
|
Elapsed_time_in_minutes: 0
|
|
Elapsed_time_in_hours: 0
|
|
Elapsed_time_in_days: 0
|
|
|
|
Virtual_time_in_seconds: 0.26
|
|
Virtual_time_in_minutes: 0.00433333
|
|
Virtual_time_in_hours: 7.22222e-05
|
|
Virtual_time_in_days: 3.00926e-06
|
|
|
|
Ruby_current_time: 213131
|
|
Ruby_start_time: 0
|
|
Ruby_cycles: 213131
|
|
|
|
mbytes_resident: 35.9023
|
|
mbytes_total: 232.609
|
|
resident_ratio: 0.154396
|
|
|
|
ruby_cycles_executed: [ 213132 ]
|
|
|
|
Busy Controller Counts:
|
|
L1Cache-0:0
|
|
Directory-0:0
|
|
|
|
|
|
Busy Bank Count:0
|
|
|
|
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 978 average: 15.7883 | standard deviation: 1.14907 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 4 82 879 ]
|
|
|
|
All Non-Zero Cycle Demand Cache Accesses
|
|
----------------------------------------
|
|
miss_latency: [binsize: 64 max: 6858 count: 963 average: 3505.41 | standard deviation: 1666 | 67 16 4 2 10 5 22 17 6 9 5 8 4 2 4 3 0 1 0 1 2 1 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 5 5 4 4 12 9 13 24 17 17 29 22 26 32 30 39 37 41 29 39 32 34 28 34 30 27 28 19 18 10 3 7 12 5 7 7 4 7 1 5 3 3 3 2 0 0 0 1 2 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
|
miss_latency_LD: [binsize: 32 max: 6253 count: 51 average: 3926.14 | standard deviation: 1480.7 | 3 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 1 1 0 1 0 0 3 0 1 1 0 0 0 0 0 1 1 0 2 0 3 1 1 1 0 2 2 1 0 0 0 1 0 0 2 1 3 3 0 1 0 0 0 1 0 0 2 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
|
miss_latency_ST: [binsize: 64 max: 6858 count: 863 average: 3652.34 | standard deviation: 1553.9 | 60 13 3 2 7 3 9 13 1 7 0 4 1 2 3 1 0 1 0 1 2 1 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 5 5 4 4 12 8 13 21 16 16 26 21 25 32 30 37 35 38 27 38 28 33 28 33 28 23 25 18 18 9 1 7 10 5 7 7 4 7 0 5 3 2 3 2 0 0 0 1 2 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
|
miss_latency_IFETCH: [binsize: 8 max: 1022 count: 49 average: 479.796 | standard deviation: 243.565 | 4 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 1 0 0 0 0 1 4 3 1 1 0 2 1 0 0 0 0 0 0 0 3 1 2 0 1 0 1 0 0 1 0 0 0 1 1 0 0 0 0 2 0 0 1 0 0 2 1 0 1 0 0 0 2 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 ]
|
|
miss_latency_L1Cache: [binsize: 1 max: 114 count: 72 average: 17.4167 | standard deviation: 35.9832 | 0 9 9 12 32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 1 2 0 0 1 0 0 0 1 ]
|
|
miss_latency_L2Cache: [binsize: 32 max: 5339 count: 41 average: 2283.05 | standard deviation: 1908.79 | 5 0 0 6 0 0 2 0 0 0 0 1 0 0 1 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 1 0 0 1 1 2 0 0 1 0 1 0 1 0 1 1 0 2 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
|
miss_latency_Directory: [binsize: 64 max: 6858 count: 850 average: 3859.83 | standard deviation: 1320.43 | 0 0 4 0 10 4 22 15 6 8 5 8 3 2 4 3 0 1 0 1 2 1 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 4 3 3 4 11 9 12 23 17 15 27 21 25 31 29 38 35 41 29 39 32 33 28 32 30 27 28 19 18 9 3 7 12 5 7 6 4 7 1 5 3 3 3 2 0 0 0 1 2 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
|
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
imcomplete_wCC_Times: 0
|
|
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
imcomplete_dir_Times: 850
|
|
miss_latency_LD_L1Cache: [binsize: 1 max: 103 count: 4 average: 27.75 | standard deviation: 50.183 | 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
|
miss_latency_LD_Directory: [binsize: 32 max: 6253 count: 47 average: 4257.91 | standard deviation: 974.148 | 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 1 1 0 1 0 0 3 0 1 1 0 0 0 0 0 1 1 0 2 0 3 1 1 1 0 2 2 1 0 0 0 1 0 0 2 1 3 3 0 1 0 0 0 1 0 0 2 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
|
miss_latency_ST_L1Cache: [binsize: 1 max: 114 count: 66 average: 17.197 | standard deviation: 35.8598 | 0 8 9 11 29 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 1 1 2 0 0 1 0 0 0 1 ]
|
|
miss_latency_ST_L2Cache: [binsize: 32 max: 5339 count: 37 average: 2523.57 | standard deviation: 1854.34 | 3 0 0 4 0 0 2 0 0 0 0 1 0 0 1 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 1 0 0 1 1 2 0 0 1 0 1 0 1 0 1 1 0 2 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
|
miss_latency_ST_Directory: [binsize: 64 max: 6858 count: 760 average: 4022.97 | standard deviation: 1109.22 | 0 0 3 0 7 2 9 11 1 6 0 4 0 2 3 1 0 1 0 1 2 1 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 4 3 3 4 11 8 12 20 16 14 24 20 24 31 29 36 33 38 27 38 28 32 28 31 28 23 25 18 18 8 1 7 10 5 7 6 4 7 0 5 3 2 3 2 0 0 0 1 2 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
|
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 4 count: 2 average: 4 | standard deviation: 0 | 0 0 0 0 2 ]
|
|
miss_latency_IFETCH_L2Cache: [binsize: 1 max: 112 count: 4 average: 58.25 | standard deviation: 60.9289 | 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 ]
|
|
miss_latency_IFETCH_Directory: [binsize: 8 max: 1022 count: 43 average: 541.14 | standard deviation: 189.677 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 1 0 0 0 0 1 4 3 1 1 0 2 1 0 0 0 0 0 0 0 3 1 2 0 1 0 1 0 0 1 0 0 0 1 1 0 0 0 0 2 0 0 1 0 0 2 1 0 1 0 0 0 2 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 ]
|
|
|
|
All Non-Zero Cycle SW Prefetch Requests
|
|
------------------------------------
|
|
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
Request vs. RubySystem State Profile
|
|
--------------------------------
|
|
|
|
|
|
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
|
|
Message Delayed Cycles
|
|
----------------------
|
|
Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
|
|
Resource Usage
|
|
--------------
|
|
page_size: 4096
|
|
user_time: 0
|
|
system_time: 0
|
|
page_reclaims: 10130
|
|
page_faults: 0
|
|
swaps: 0
|
|
block_inputs: 0
|
|
block_outputs: 0
|
|
|
|
Network Stats
|
|
-------------
|
|
|
|
total_msg_count_Request_Control: 2553 20424
|
|
total_msg_count_Response_Data: 2550 183600
|
|
total_msg_count_Writeback_Data: 2292 165024
|
|
total_msg_count_Writeback_Control: 5291 42328
|
|
total_msg_count_Unblock_Control: 2546 20368
|
|
total_msgs: 15232 total_bytes: 431744
|
|
|
|
switch_0_inlinks: 2
|
|
switch_0_outlinks: 2
|
|
links_utilized_percent_switch_0: 2.11044
|
|
links_utilized_percent_switch_0_link_0: 1.9922 bw: 16000 base_latency: 1
|
|
links_utilized_percent_switch_0_link_1: 2.22868 bw: 16000 base_latency: 1
|
|
|
|
outgoing_messages_switch_0_link_0_Response_Data: 850 61200 [ 0 0 0 0 850 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_0_link_0_Writeback_Control: 842 6736 [ 0 0 0 842 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_0_link_1_Request_Control: 852 6816 [ 0 0 852 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_0_link_1_Writeback_Data: 764 55008 [ 0 0 0 0 0 764 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_0_link_1_Writeback_Control: 923 7384 [ 0 0 845 0 0 78 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_0_link_1_Unblock_Control: 849 6792 [ 0 0 0 0 0 849 0 0 0 0 ] base_latency: 1
|
|
|
|
switch_1_inlinks: 2
|
|
switch_1_outlinks: 2
|
|
links_utilized_percent_switch_1: 2.10985
|
|
links_utilized_percent_switch_1_link_0: 2.2275 bw: 16000 base_latency: 1
|
|
links_utilized_percent_switch_1_link_1: 1.9922 bw: 16000 base_latency: 1
|
|
|
|
outgoing_messages_switch_1_link_0_Request_Control: 850 6800 [ 0 0 850 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_1_link_0_Writeback_Data: 764 55008 [ 0 0 0 0 0 764 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_1_link_0_Writeback_Control: 921 7368 [ 0 0 843 0 0 78 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_1_link_0_Unblock_Control: 848 6784 [ 0 0 0 0 0 848 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_1_link_1_Response_Data: 850 61200 [ 0 0 0 0 850 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_1_link_1_Writeback_Control: 842 6736 [ 0 0 0 842 0 0 0 0 0 0 ] base_latency: 1
|
|
|
|
switch_2_inlinks: 2
|
|
switch_2_outlinks: 2
|
|
links_utilized_percent_switch_2: 2.11009
|
|
links_utilized_percent_switch_2_link_0: 1.9922 bw: 16000 base_latency: 1
|
|
links_utilized_percent_switch_2_link_1: 2.22797 bw: 16000 base_latency: 1
|
|
|
|
outgoing_messages_switch_2_link_0_Response_Data: 850 61200 [ 0 0 0 0 850 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_2_link_0_Writeback_Control: 842 6736 [ 0 0 0 842 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_2_link_1_Request_Control: 851 6808 [ 0 0 851 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_2_link_1_Writeback_Data: 764 55008 [ 0 0 0 0 0 764 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_2_link_1_Writeback_Control: 921 7368 [ 0 0 843 0 0 78 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_2_link_1_Unblock_Control: 849 6792 [ 0 0 0 0 0 849 0 0 0 0 ] base_latency: 1
|
|
|
|
Cache Stats: system.l1_cntrl0.L1IcacheMemory
|
|
system.l1_cntrl0.L1IcacheMemory_total_misses: 47
|
|
system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 47
|
|
system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
|
|
system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
|
|
system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
|
|
|
|
system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100%
|
|
|
|
system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 47 100%
|
|
|
|
Cache Stats: system.l1_cntrl0.L1DcacheMemory
|
|
system.l1_cntrl0.L1DcacheMemory_total_misses: 846
|
|
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 846
|
|
system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
|
|
system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
|
|
system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
|
|
|
|
system.l1_cntrl0.L1DcacheMemory_request_type_LD: 5.55556%
|
|
system.l1_cntrl0.L1DcacheMemory_request_type_ST: 94.4444%
|
|
|
|
system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 846 100%
|
|
|
|
Cache Stats: system.l1_cntrl0.L2cacheMemory
|
|
system.l1_cntrl0.L2cacheMemory_total_misses: 893
|
|
system.l1_cntrl0.L2cacheMemory_total_demand_misses: 893
|
|
system.l1_cntrl0.L2cacheMemory_total_prefetches: 0
|
|
system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0
|
|
system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0
|
|
|
|
system.l1_cntrl0.L2cacheMemory_request_type_LD: 5.26316%
|
|
system.l1_cntrl0.L2cacheMemory_request_type_ST: 89.4737%
|
|
system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 5.26316%
|
|
|
|
system.l1_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 893 100%
|
|
|
|
--- L1Cache ---
|
|
- Event Counts -
|
|
Load [51 ] 51
|
|
Ifetch [52 ] 52
|
|
Store [889 ] 889
|
|
L2_Replacement [845 ] 845
|
|
L1_to_L2 [15901 ] 15901
|
|
Trigger_L2_to_L1D [37 ] 37
|
|
Trigger_L2_to_L1I [4 ] 4
|
|
Complete_L2_to_L1 [41 ] 41
|
|
Other_GETX [0 ] 0
|
|
Other_GETS [0 ] 0
|
|
Merged_GETS [0 ] 0
|
|
Other_GETS_No_Mig [0 ] 0
|
|
NC_DMA_GETS [0 ] 0
|
|
Invalidate [0 ] 0
|
|
Ack [0 ] 0
|
|
Shared_Ack [0 ] 0
|
|
Data [0 ] 0
|
|
Shared_Data [0 ] 0
|
|
Exclusive_Data [850 ] 850
|
|
Writeback_Ack [842 ] 842
|
|
Writeback_Nack [0 ] 0
|
|
All_acks [0 ] 0
|
|
All_acks_no_sharers [850 ] 850
|
|
Flush_line [0 ] 0
|
|
Block_Ack [0 ] 0
|
|
|
|
- Transitions -
|
|
I Load [47 ] 47
|
|
I Ifetch [43 ] 43
|
|
I Store [762 ] 762
|
|
I L2_Replacement [0 ] 0
|
|
I L1_to_L2 [0 ] 0
|
|
I Trigger_L2_to_L1D [0 ] 0
|
|
I Trigger_L2_to_L1I [0 ] 0
|
|
I Other_GETX [0 ] 0
|
|
I Other_GETS [0 ] 0
|
|
I Other_GETS_No_Mig [0 ] 0
|
|
I NC_DMA_GETS [0 ] 0
|
|
I Invalidate [0 ] 0
|
|
I Flush_line [0 ] 0
|
|
|
|
S Load [0 ] 0
|
|
S Ifetch [0 ] 0
|
|
S Store [0 ] 0
|
|
S L2_Replacement [0 ] 0
|
|
S L1_to_L2 [0 ] 0
|
|
S Trigger_L2_to_L1D [0 ] 0
|
|
S Trigger_L2_to_L1I [0 ] 0
|
|
S Other_GETX [0 ] 0
|
|
S Other_GETS [0 ] 0
|
|
S Other_GETS_No_Mig [0 ] 0
|
|
S NC_DMA_GETS [0 ] 0
|
|
S Invalidate [0 ] 0
|
|
S Flush_line [0 ] 0
|
|
|
|
O Load [0 ] 0
|
|
O Ifetch [0 ] 0
|
|
O Store [0 ] 0
|
|
O L2_Replacement [0 ] 0
|
|
O L1_to_L2 [0 ] 0
|
|
O Trigger_L2_to_L1D [0 ] 0
|
|
O Trigger_L2_to_L1I [0 ] 0
|
|
O Other_GETX [0 ] 0
|
|
O Other_GETS [0 ] 0
|
|
O Merged_GETS [0 ] 0
|
|
O Other_GETS_No_Mig [0 ] 0
|
|
O NC_DMA_GETS [0 ] 0
|
|
O Invalidate [0 ] 0
|
|
O Flush_line [0 ] 0
|
|
|
|
M Load [0 ] 0
|
|
M Ifetch [1 ] 1
|
|
M Store [0 ] 0
|
|
M L2_Replacement [79 ] 79
|
|
M L1_to_L2 [88 ] 88
|
|
M Trigger_L2_to_L1D [9 ] 9
|
|
M Trigger_L2_to_L1I [0 ] 0
|
|
M Other_GETX [0 ] 0
|
|
M Other_GETS [0 ] 0
|
|
M Merged_GETS [0 ] 0
|
|
M Other_GETS_No_Mig [0 ] 0
|
|
M NC_DMA_GETS [0 ] 0
|
|
M Invalidate [0 ] 0
|
|
M Flush_line [0 ] 0
|
|
|
|
MM Load [4 ] 4
|
|
MM Ifetch [1 ] 1
|
|
MM Store [65 ] 65
|
|
MM L2_Replacement [766 ] 766
|
|
MM L1_to_L2 [800 ] 800
|
|
MM Trigger_L2_to_L1D [28 ] 28
|
|
MM Trigger_L2_to_L1I [4 ] 4
|
|
MM Other_GETX [0 ] 0
|
|
MM Other_GETS [0 ] 0
|
|
MM Merged_GETS [0 ] 0
|
|
MM Other_GETS_No_Mig [0 ] 0
|
|
MM NC_DMA_GETS [0 ] 0
|
|
MM Invalidate [0 ] 0
|
|
MM Flush_line [0 ] 0
|
|
|
|
IR Load [0 ] 0
|
|
IR Ifetch [0 ] 0
|
|
IR Store [0 ] 0
|
|
IR L1_to_L2 [0 ] 0
|
|
IR Flush_line [0 ] 0
|
|
|
|
SR Load [0 ] 0
|
|
SR Ifetch [0 ] 0
|
|
SR Store [0 ] 0
|
|
SR L1_to_L2 [0 ] 0
|
|
SR Flush_line [0 ] 0
|
|
|
|
OR Load [0 ] 0
|
|
OR Ifetch [0 ] 0
|
|
OR Store [0 ] 0
|
|
OR L1_to_L2 [0 ] 0
|
|
OR Flush_line [0 ] 0
|
|
|
|
MR Load [0 ] 0
|
|
MR Ifetch [0 ] 0
|
|
MR Store [9 ] 9
|
|
MR L1_to_L2 [43 ] 43
|
|
MR Flush_line [0 ] 0
|
|
|
|
MMR Load [0 ] 0
|
|
MMR Ifetch [4 ] 4
|
|
MMR Store [28 ] 28
|
|
MMR L1_to_L2 [78 ] 78
|
|
MMR Flush_line [0 ] 0
|
|
|
|
IM Load [0 ] 0
|
|
IM Ifetch [0 ] 0
|
|
IM Store [0 ] 0
|
|
IM L2_Replacement [0 ] 0
|
|
IM L1_to_L2 [9451 ] 9451
|
|
IM Other_GETX [0 ] 0
|
|
IM Other_GETS [0 ] 0
|
|
IM Other_GETS_No_Mig [0 ] 0
|
|
IM NC_DMA_GETS [0 ] 0
|
|
IM Invalidate [0 ] 0
|
|
IM Ack [0 ] 0
|
|
IM Data [0 ] 0
|
|
IM Exclusive_Data [760 ] 760
|
|
IM Flush_line [0 ] 0
|
|
|
|
SM Load [0 ] 0
|
|
SM Ifetch [0 ] 0
|
|
SM Store [0 ] 0
|
|
SM L2_Replacement [0 ] 0
|
|
SM L1_to_L2 [0 ] 0
|
|
SM Other_GETX [0 ] 0
|
|
SM Other_GETS [0 ] 0
|
|
SM Other_GETS_No_Mig [0 ] 0
|
|
SM NC_DMA_GETS [0 ] 0
|
|
SM Invalidate [0 ] 0
|
|
SM Ack [0 ] 0
|
|
SM Data [0 ] 0
|
|
SM Exclusive_Data [0 ] 0
|
|
SM Flush_line [0 ] 0
|
|
|
|
OM Load [0 ] 0
|
|
OM Ifetch [0 ] 0
|
|
OM Store [0 ] 0
|
|
OM L2_Replacement [0 ] 0
|
|
OM L1_to_L2 [0 ] 0
|
|
OM Other_GETX [0 ] 0
|
|
OM Other_GETS [0 ] 0
|
|
OM Merged_GETS [0 ] 0
|
|
OM Other_GETS_No_Mig [0 ] 0
|
|
OM NC_DMA_GETS [0 ] 0
|
|
OM Invalidate [0 ] 0
|
|
OM Ack [0 ] 0
|
|
OM All_acks [0 ] 0
|
|
OM All_acks_no_sharers [0 ] 0
|
|
OM Flush_line [0 ] 0
|
|
|
|
ISM Load [0 ] 0
|
|
ISM Ifetch [0 ] 0
|
|
ISM Store [0 ] 0
|
|
ISM L2_Replacement [0 ] 0
|
|
ISM L1_to_L2 [0 ] 0
|
|
ISM Ack [0 ] 0
|
|
ISM All_acks_no_sharers [0 ] 0
|
|
ISM Flush_line [0 ] 0
|
|
|
|
M_W Load [0 ] 0
|
|
M_W Ifetch [0 ] 0
|
|
M_W Store [0 ] 0
|
|
M_W L2_Replacement [0 ] 0
|
|
M_W L1_to_L2 [239 ] 239
|
|
M_W Ack [0 ] 0
|
|
M_W All_acks_no_sharers [90 ] 90
|
|
M_W Flush_line [0 ] 0
|
|
|
|
MM_W Load [0 ] 0
|
|
MM_W Ifetch [0 ] 0
|
|
MM_W Store [1 ] 1
|
|
MM_W L2_Replacement [0 ] 0
|
|
MM_W L1_to_L2 [4486 ] 4486
|
|
MM_W Ack [0 ] 0
|
|
MM_W All_acks_no_sharers [760 ] 760
|
|
MM_W Flush_line [0 ] 0
|
|
|
|
IS Load [0 ] 0
|
|
IS Ifetch [0 ] 0
|
|
IS Store [0 ] 0
|
|
IS L2_Replacement [0 ] 0
|
|
IS L1_to_L2 [611 ] 611
|
|
IS Other_GETX [0 ] 0
|
|
IS Other_GETS [0 ] 0
|
|
IS Other_GETS_No_Mig [0 ] 0
|
|
IS NC_DMA_GETS [0 ] 0
|
|
IS Invalidate [0 ] 0
|
|
IS Ack [0 ] 0
|
|
IS Shared_Ack [0 ] 0
|
|
IS Data [0 ] 0
|
|
IS Shared_Data [0 ] 0
|
|
IS Exclusive_Data [90 ] 90
|
|
IS Flush_line [0 ] 0
|
|
|
|
SS Load [0 ] 0
|
|
SS Ifetch [0 ] 0
|
|
SS Store [0 ] 0
|
|
SS L2_Replacement [0 ] 0
|
|
SS L1_to_L2 [0 ] 0
|
|
SS Ack [0 ] 0
|
|
SS Shared_Ack [0 ] 0
|
|
SS All_acks [0 ] 0
|
|
SS All_acks_no_sharers [0 ] 0
|
|
SS Flush_line [0 ] 0
|
|
|
|
OI Load [0 ] 0
|
|
OI Ifetch [0 ] 0
|
|
OI Store [0 ] 0
|
|
OI L2_Replacement [0 ] 0
|
|
OI L1_to_L2 [0 ] 0
|
|
OI Other_GETX [0 ] 0
|
|
OI Other_GETS [0 ] 0
|
|
OI Merged_GETS [0 ] 0
|
|
OI Other_GETS_No_Mig [0 ] 0
|
|
OI NC_DMA_GETS [0 ] 0
|
|
OI Invalidate [0 ] 0
|
|
OI Writeback_Ack [0 ] 0
|
|
OI Flush_line [0 ] 0
|
|
|
|
MI Load [0 ] 0
|
|
MI Ifetch [1 ] 1
|
|
MI Store [2 ] 2
|
|
MI L2_Replacement [0 ] 0
|
|
MI L1_to_L2 [0 ] 0
|
|
MI Other_GETX [0 ] 0
|
|
MI Other_GETS [0 ] 0
|
|
MI Merged_GETS [0 ] 0
|
|
MI Other_GETS_No_Mig [0 ] 0
|
|
MI NC_DMA_GETS [0 ] 0
|
|
MI Invalidate [0 ] 0
|
|
MI Writeback_Ack [842 ] 842
|
|
MI Flush_line [0 ] 0
|
|
|
|
II Load [0 ] 0
|
|
II Ifetch [0 ] 0
|
|
II Store [0 ] 0
|
|
II L2_Replacement [0 ] 0
|
|
II L1_to_L2 [0 ] 0
|
|
II Other_GETX [0 ] 0
|
|
II Other_GETS [0 ] 0
|
|
II Other_GETS_No_Mig [0 ] 0
|
|
II NC_DMA_GETS [0 ] 0
|
|
II Invalidate [0 ] 0
|
|
II Writeback_Ack [0 ] 0
|
|
II Writeback_Nack [0 ] 0
|
|
II Flush_line [0 ] 0
|
|
|
|
IT Load [0 ] 0
|
|
IT Ifetch [0 ] 0
|
|
IT Store [0 ] 0
|
|
IT L2_Replacement [0 ] 0
|
|
IT L1_to_L2 [0 ] 0
|
|
IT Complete_L2_to_L1 [0 ] 0
|
|
|
|
ST Load [0 ] 0
|
|
ST Ifetch [0 ] 0
|
|
ST Store [0 ] 0
|
|
ST L2_Replacement [0 ] 0
|
|
ST L1_to_L2 [0 ] 0
|
|
ST Complete_L2_to_L1 [0 ] 0
|
|
|
|
OT Load [0 ] 0
|
|
OT Ifetch [0 ] 0
|
|
OT Store [0 ] 0
|
|
OT L2_Replacement [0 ] 0
|
|
OT L1_to_L2 [0 ] 0
|
|
OT Complete_L2_to_L1 [0 ] 0
|
|
|
|
MT Load [0 ] 0
|
|
MT Ifetch [0 ] 0
|
|
MT Store [3 ] 3
|
|
MT L2_Replacement [0 ] 0
|
|
MT L1_to_L2 [81 ] 81
|
|
MT Complete_L2_to_L1 [9 ] 9
|
|
|
|
MMT Load [0 ] 0
|
|
MMT Ifetch [2 ] 2
|
|
MMT Store [19 ] 19
|
|
MMT L2_Replacement [0 ] 0
|
|
MMT L1_to_L2 [24 ] 24
|
|
MMT Complete_L2_to_L1 [32 ] 32
|
|
|
|
MI_F Load [0 ] 0
|
|
MI_F Ifetch [0 ] 0
|
|
MI_F Store [0 ] 0
|
|
MI_F L1_to_L2 [0 ] 0
|
|
MI_F Writeback_Ack [0 ] 0
|
|
MI_F Flush_line [0 ] 0
|
|
|
|
MM_F Load [0 ] 0
|
|
MM_F Ifetch [0 ] 0
|
|
MM_F Store [0 ] 0
|
|
MM_F L1_to_L2 [0 ] 0
|
|
MM_F Other_GETX [0 ] 0
|
|
MM_F Other_GETS [0 ] 0
|
|
MM_F Merged_GETS [0 ] 0
|
|
MM_F Other_GETS_No_Mig [0 ] 0
|
|
MM_F NC_DMA_GETS [0 ] 0
|
|
MM_F Invalidate [0 ] 0
|
|
MM_F Ack [0 ] 0
|
|
MM_F All_acks [0 ] 0
|
|
MM_F All_acks_no_sharers [0 ] 0
|
|
MM_F Flush_line [0 ] 0
|
|
MM_F Block_Ack [0 ] 0
|
|
|
|
IM_F Load [0 ] 0
|
|
IM_F Ifetch [0 ] 0
|
|
IM_F Store [0 ] 0
|
|
IM_F L2_Replacement [0 ] 0
|
|
IM_F L1_to_L2 [0 ] 0
|
|
IM_F Other_GETX [0 ] 0
|
|
IM_F Other_GETS [0 ] 0
|
|
IM_F Other_GETS_No_Mig [0 ] 0
|
|
IM_F NC_DMA_GETS [0 ] 0
|
|
IM_F Invalidate [0 ] 0
|
|
IM_F Ack [0 ] 0
|
|
IM_F Data [0 ] 0
|
|
IM_F Exclusive_Data [0 ] 0
|
|
IM_F Flush_line [0 ] 0
|
|
|
|
ISM_F Load [0 ] 0
|
|
ISM_F Ifetch [0 ] 0
|
|
ISM_F Store [0 ] 0
|
|
ISM_F L2_Replacement [0 ] 0
|
|
ISM_F L1_to_L2 [0 ] 0
|
|
ISM_F Ack [0 ] 0
|
|
ISM_F All_acks_no_sharers [0 ] 0
|
|
ISM_F Flush_line [0 ] 0
|
|
|
|
SM_F Load [0 ] 0
|
|
SM_F Ifetch [0 ] 0
|
|
SM_F Store [0 ] 0
|
|
SM_F L2_Replacement [0 ] 0
|
|
SM_F L1_to_L2 [0 ] 0
|
|
SM_F Other_GETX [0 ] 0
|
|
SM_F Other_GETS [0 ] 0
|
|
SM_F Other_GETS_No_Mig [0 ] 0
|
|
SM_F NC_DMA_GETS [0 ] 0
|
|
SM_F Invalidate [0 ] 0
|
|
SM_F Ack [0 ] 0
|
|
SM_F Data [0 ] 0
|
|
SM_F Exclusive_Data [0 ] 0
|
|
SM_F Flush_line [0 ] 0
|
|
|
|
OM_F Load [0 ] 0
|
|
OM_F Ifetch [0 ] 0
|
|
OM_F Store [0 ] 0
|
|
OM_F L2_Replacement [0 ] 0
|
|
OM_F L1_to_L2 [0 ] 0
|
|
OM_F Other_GETX [0 ] 0
|
|
OM_F Other_GETS [0 ] 0
|
|
OM_F Merged_GETS [0 ] 0
|
|
OM_F Other_GETS_No_Mig [0 ] 0
|
|
OM_F NC_DMA_GETS [0 ] 0
|
|
OM_F Invalidate [0 ] 0
|
|
OM_F Ack [0 ] 0
|
|
OM_F All_acks [0 ] 0
|
|
OM_F All_acks_no_sharers [0 ] 0
|
|
OM_F Flush_line [0 ] 0
|
|
|
|
MM_WF Load [0 ] 0
|
|
MM_WF Ifetch [0 ] 0
|
|
MM_WF Store [0 ] 0
|
|
MM_WF L2_Replacement [0 ] 0
|
|
MM_WF L1_to_L2 [0 ] 0
|
|
MM_WF Ack [0 ] 0
|
|
MM_WF All_acks_no_sharers [0 ] 0
|
|
MM_WF Flush_line [0 ] 0
|
|
|
|
Cache Stats: system.dir_cntrl0.probeFilter
|
|
system.dir_cntrl0.probeFilter_total_misses: 0
|
|
system.dir_cntrl0.probeFilter_total_demand_misses: 0
|
|
system.dir_cntrl0.probeFilter_total_prefetches: 0
|
|
system.dir_cntrl0.probeFilter_total_sw_prefetches: 0
|
|
system.dir_cntrl0.probeFilter_total_hw_prefetches: 0
|
|
|
|
|
|
Memory controller: system.dir_cntrl0.memBuffer:
|
|
memory_total_requests: 1614
|
|
memory_reads: 850
|
|
memory_writes: 764
|
|
memory_refreshes: 444
|
|
memory_total_request_delays: 1136
|
|
memory_delays_per_request: 0.703841
|
|
memory_delays_in_input_queue: 148
|
|
memory_delays_behind_head_of_bank_queue: 4
|
|
memory_delays_stalled_at_head_of_bank_queue: 984
|
|
memory_stalls_for_bank_busy: 278
|
|
memory_stalls_for_random_busy: 0
|
|
memory_stalls_for_anti_starvation: 0
|
|
memory_stalls_for_arbitration: 71
|
|
memory_stalls_for_bus: 363
|
|
memory_stalls_for_tfaw: 0
|
|
memory_stalls_for_read_write_turnaround: 151
|
|
memory_stalls_for_read_read_turnaround: 121
|
|
accesses_per_bank: 44 58 47 90 75 58 58 48 47 49 56 50 32 37 53 44 53 47 48 55 53 40 39 41 34 44 54 59 55 47 50 49
|
|
|
|
--- Directory ---
|
|
- Event Counts -
|
|
GETX [760 ] 760
|
|
GETS [91 ] 91
|
|
PUT [889 ] 889
|
|
Unblock [0 ] 0
|
|
UnblockS [0 ] 0
|
|
UnblockM [848 ] 848
|
|
Writeback_Clean [0 ] 0
|
|
Writeback_Dirty [0 ] 0
|
|
Writeback_Exclusive_Clean [78 ] 78
|
|
Writeback_Exclusive_Dirty [764 ] 764
|
|
Pf_Replacement [0 ] 0
|
|
DMA_READ [0 ] 0
|
|
DMA_WRITE [0 ] 0
|
|
Memory_Data [850 ] 850
|
|
Memory_Ack [763 ] 763
|
|
Ack [0 ] 0
|
|
Shared_Ack [0 ] 0
|
|
Shared_Data [0 ] 0
|
|
Data [0 ] 0
|
|
Exclusive_Data [0 ] 0
|
|
All_acks_and_shared_data [0 ] 0
|
|
All_acks_and_owner_data [0 ] 0
|
|
All_acks_and_data_no_sharers [0 ] 0
|
|
All_Unblocks [0 ] 0
|
|
GETF [0 ] 0
|
|
PUTF [0 ] 0
|
|
|
|
- Transitions -
|
|
NX GETX [0 ] 0
|
|
NX GETS [0 ] 0
|
|
NX PUT [0 ] 0
|
|
NX Pf_Replacement [0 ] 0
|
|
NX DMA_READ [0 ] 0
|
|
NX DMA_WRITE [0 ] 0
|
|
NX GETF [0 ] 0
|
|
|
|
NO GETX [0 ] 0
|
|
NO GETS [0 ] 0
|
|
NO PUT [842 ] 842
|
|
NO Pf_Replacement [0 ] 0
|
|
NO DMA_READ [0 ] 0
|
|
NO DMA_WRITE [0 ] 0
|
|
NO GETF [0 ] 0
|
|
|
|
S GETX [0 ] 0
|
|
S GETS [0 ] 0
|
|
S PUT [0 ] 0
|
|
S Pf_Replacement [0 ] 0
|
|
S DMA_READ [0 ] 0
|
|
S DMA_WRITE [0 ] 0
|
|
S GETF [0 ] 0
|
|
|
|
O GETX [0 ] 0
|
|
O GETS [0 ] 0
|
|
O PUT [0 ] 0
|
|
O Pf_Replacement [0 ] 0
|
|
O DMA_READ [0 ] 0
|
|
O DMA_WRITE [0 ] 0
|
|
O GETF [0 ] 0
|
|
|
|
E GETX [760 ] 760
|
|
E GETS [90 ] 90
|
|
E PUT [0 ] 0
|
|
E DMA_READ [0 ] 0
|
|
E DMA_WRITE [0 ] 0
|
|
E GETF [0 ] 0
|
|
|
|
O_R GETX [0 ] 0
|
|
O_R GETS [0 ] 0
|
|
O_R PUT [0 ] 0
|
|
O_R Pf_Replacement [0 ] 0
|
|
O_R DMA_READ [0 ] 0
|
|
O_R DMA_WRITE [0 ] 0
|
|
O_R Ack [0 ] 0
|
|
O_R All_acks_and_data_no_sharers [0 ] 0
|
|
O_R GETF [0 ] 0
|
|
|
|
S_R GETX [0 ] 0
|
|
S_R GETS [0 ] 0
|
|
S_R PUT [0 ] 0
|
|
S_R Pf_Replacement [0 ] 0
|
|
S_R DMA_READ [0 ] 0
|
|
S_R DMA_WRITE [0 ] 0
|
|
S_R Ack [0 ] 0
|
|
S_R Data [0 ] 0
|
|
S_R All_acks_and_data_no_sharers [0 ] 0
|
|
S_R GETF [0 ] 0
|
|
|
|
NO_R GETX [0 ] 0
|
|
NO_R GETS [0 ] 0
|
|
NO_R PUT [0 ] 0
|
|
NO_R Pf_Replacement [0 ] 0
|
|
NO_R DMA_READ [0 ] 0
|
|
NO_R DMA_WRITE [0 ] 0
|
|
NO_R Ack [0 ] 0
|
|
NO_R Data [0 ] 0
|
|
NO_R Exclusive_Data [0 ] 0
|
|
NO_R All_acks_and_data_no_sharers [0 ] 0
|
|
NO_R GETF [0 ] 0
|
|
|
|
NO_B GETX [0 ] 0
|
|
NO_B GETS [0 ] 0
|
|
NO_B PUT [47 ] 47
|
|
NO_B UnblockS [0 ] 0
|
|
NO_B UnblockM [848 ] 848
|
|
NO_B Pf_Replacement [0 ] 0
|
|
NO_B DMA_READ [0 ] 0
|
|
NO_B DMA_WRITE [0 ] 0
|
|
NO_B GETF [0 ] 0
|
|
|
|
NO_B_X GETX [0 ] 0
|
|
NO_B_X GETS [0 ] 0
|
|
NO_B_X PUT [0 ] 0
|
|
NO_B_X UnblockS [0 ] 0
|
|
NO_B_X UnblockM [0 ] 0
|
|
NO_B_X Pf_Replacement [0 ] 0
|
|
NO_B_X DMA_READ [0 ] 0
|
|
NO_B_X DMA_WRITE [0 ] 0
|
|
NO_B_X GETF [0 ] 0
|
|
|
|
NO_B_S GETX [0 ] 0
|
|
NO_B_S GETS [0 ] 0
|
|
NO_B_S PUT [0 ] 0
|
|
NO_B_S UnblockS [0 ] 0
|
|
NO_B_S UnblockM [0 ] 0
|
|
NO_B_S Pf_Replacement [0 ] 0
|
|
NO_B_S DMA_READ [0 ] 0
|
|
NO_B_S DMA_WRITE [0 ] 0
|
|
NO_B_S GETF [0 ] 0
|
|
|
|
NO_B_S_W GETX [0 ] 0
|
|
NO_B_S_W GETS [0 ] 0
|
|
NO_B_S_W PUT [0 ] 0
|
|
NO_B_S_W UnblockS [0 ] 0
|
|
NO_B_S_W Pf_Replacement [0 ] 0
|
|
NO_B_S_W DMA_READ [0 ] 0
|
|
NO_B_S_W DMA_WRITE [0 ] 0
|
|
NO_B_S_W All_Unblocks [0 ] 0
|
|
NO_B_S_W GETF [0 ] 0
|
|
|
|
O_B GETX [0 ] 0
|
|
O_B GETS [0 ] 0
|
|
O_B PUT [0 ] 0
|
|
O_B UnblockS [0 ] 0
|
|
O_B UnblockM [0 ] 0
|
|
O_B Pf_Replacement [0 ] 0
|
|
O_B DMA_READ [0 ] 0
|
|
O_B DMA_WRITE [0 ] 0
|
|
O_B GETF [0 ] 0
|
|
|
|
NO_B_W GETX [0 ] 0
|
|
NO_B_W GETS [0 ] 0
|
|
NO_B_W PUT [0 ] 0
|
|
NO_B_W UnblockS [0 ] 0
|
|
NO_B_W UnblockM [0 ] 0
|
|
NO_B_W Pf_Replacement [0 ] 0
|
|
NO_B_W DMA_READ [0 ] 0
|
|
NO_B_W DMA_WRITE [0 ] 0
|
|
NO_B_W Memory_Data [850 ] 850
|
|
NO_B_W GETF [0 ] 0
|
|
|
|
O_B_W GETX [0 ] 0
|
|
O_B_W GETS [0 ] 0
|
|
O_B_W PUT [0 ] 0
|
|
O_B_W UnblockS [0 ] 0
|
|
O_B_W Pf_Replacement [0 ] 0
|
|
O_B_W DMA_READ [0 ] 0
|
|
O_B_W DMA_WRITE [0 ] 0
|
|
O_B_W Memory_Data [0 ] 0
|
|
O_B_W GETF [0 ] 0
|
|
|
|
NO_W GETX [0 ] 0
|
|
NO_W GETS [0 ] 0
|
|
NO_W PUT [0 ] 0
|
|
NO_W Pf_Replacement [0 ] 0
|
|
NO_W DMA_READ [0 ] 0
|
|
NO_W DMA_WRITE [0 ] 0
|
|
NO_W Memory_Data [0 ] 0
|
|
NO_W GETF [0 ] 0
|
|
|
|
O_W GETX [0 ] 0
|
|
O_W GETS [0 ] 0
|
|
O_W PUT [0 ] 0
|
|
O_W Pf_Replacement [0 ] 0
|
|
O_W DMA_READ [0 ] 0
|
|
O_W DMA_WRITE [0 ] 0
|
|
O_W Memory_Data [0 ] 0
|
|
O_W GETF [0 ] 0
|
|
|
|
NO_DW_B_W GETX [0 ] 0
|
|
NO_DW_B_W GETS [0 ] 0
|
|
NO_DW_B_W PUT [0 ] 0
|
|
NO_DW_B_W Pf_Replacement [0 ] 0
|
|
NO_DW_B_W DMA_READ [0 ] 0
|
|
NO_DW_B_W DMA_WRITE [0 ] 0
|
|
NO_DW_B_W Ack [0 ] 0
|
|
NO_DW_B_W Data [0 ] 0
|
|
NO_DW_B_W Exclusive_Data [0 ] 0
|
|
NO_DW_B_W All_acks_and_data_no_sharers [0 ] 0
|
|
NO_DW_B_W GETF [0 ] 0
|
|
|
|
NO_DR_B_W GETX [0 ] 0
|
|
NO_DR_B_W GETS [0 ] 0
|
|
NO_DR_B_W PUT [0 ] 0
|
|
NO_DR_B_W Pf_Replacement [0 ] 0
|
|
NO_DR_B_W DMA_READ [0 ] 0
|
|
NO_DR_B_W DMA_WRITE [0 ] 0
|
|
NO_DR_B_W Memory_Data [0 ] 0
|
|
NO_DR_B_W Ack [0 ] 0
|
|
NO_DR_B_W Shared_Ack [0 ] 0
|
|
NO_DR_B_W Shared_Data [0 ] 0
|
|
NO_DR_B_W Data [0 ] 0
|
|
NO_DR_B_W Exclusive_Data [0 ] 0
|
|
NO_DR_B_W GETF [0 ] 0
|
|
|
|
NO_DR_B_D GETX [0 ] 0
|
|
NO_DR_B_D GETS [0 ] 0
|
|
NO_DR_B_D PUT [0 ] 0
|
|
NO_DR_B_D Pf_Replacement [0 ] 0
|
|
NO_DR_B_D DMA_READ [0 ] 0
|
|
NO_DR_B_D DMA_WRITE [0 ] 0
|
|
NO_DR_B_D Ack [0 ] 0
|
|
NO_DR_B_D Shared_Ack [0 ] 0
|
|
NO_DR_B_D Shared_Data [0 ] 0
|
|
NO_DR_B_D Data [0 ] 0
|
|
NO_DR_B_D Exclusive_Data [0 ] 0
|
|
NO_DR_B_D All_acks_and_shared_data [0 ] 0
|
|
NO_DR_B_D All_acks_and_owner_data [0 ] 0
|
|
NO_DR_B_D All_acks_and_data_no_sharers [0 ] 0
|
|
NO_DR_B_D GETF [0 ] 0
|
|
|
|
NO_DR_B GETX [0 ] 0
|
|
NO_DR_B GETS [0 ] 0
|
|
NO_DR_B PUT [0 ] 0
|
|
NO_DR_B Pf_Replacement [0 ] 0
|
|
NO_DR_B DMA_READ [0 ] 0
|
|
NO_DR_B DMA_WRITE [0 ] 0
|
|
NO_DR_B Ack [0 ] 0
|
|
NO_DR_B Shared_Ack [0 ] 0
|
|
NO_DR_B Shared_Data [0 ] 0
|
|
NO_DR_B Data [0 ] 0
|
|
NO_DR_B Exclusive_Data [0 ] 0
|
|
NO_DR_B All_acks_and_shared_data [0 ] 0
|
|
NO_DR_B All_acks_and_owner_data [0 ] 0
|
|
NO_DR_B All_acks_and_data_no_sharers [0 ] 0
|
|
NO_DR_B GETF [0 ] 0
|
|
|
|
NO_DW_W GETX [0 ] 0
|
|
NO_DW_W GETS [0 ] 0
|
|
NO_DW_W PUT [0 ] 0
|
|
NO_DW_W Pf_Replacement [0 ] 0
|
|
NO_DW_W DMA_READ [0 ] 0
|
|
NO_DW_W DMA_WRITE [0 ] 0
|
|
NO_DW_W Memory_Ack [0 ] 0
|
|
NO_DW_W GETF [0 ] 0
|
|
|
|
O_DR_B_W GETX [0 ] 0
|
|
O_DR_B_W GETS [0 ] 0
|
|
O_DR_B_W PUT [0 ] 0
|
|
O_DR_B_W Pf_Replacement [0 ] 0
|
|
O_DR_B_W DMA_READ [0 ] 0
|
|
O_DR_B_W DMA_WRITE [0 ] 0
|
|
O_DR_B_W Memory_Data [0 ] 0
|
|
O_DR_B_W Ack [0 ] 0
|
|
O_DR_B_W Shared_Ack [0 ] 0
|
|
O_DR_B_W GETF [0 ] 0
|
|
|
|
O_DR_B GETX [0 ] 0
|
|
O_DR_B GETS [0 ] 0
|
|
O_DR_B PUT [0 ] 0
|
|
O_DR_B Pf_Replacement [0 ] 0
|
|
O_DR_B DMA_READ [0 ] 0
|
|
O_DR_B DMA_WRITE [0 ] 0
|
|
O_DR_B Ack [0 ] 0
|
|
O_DR_B Shared_Ack [0 ] 0
|
|
O_DR_B All_acks_and_owner_data [0 ] 0
|
|
O_DR_B All_acks_and_data_no_sharers [0 ] 0
|
|
O_DR_B GETF [0 ] 0
|
|
|
|
WB GETX [0 ] 0
|
|
WB GETS [1 ] 1
|
|
WB PUT [0 ] 0
|
|
WB Unblock [0 ] 0
|
|
WB Writeback_Clean [0 ] 0
|
|
WB Writeback_Dirty [0 ] 0
|
|
WB Writeback_Exclusive_Clean [78 ] 78
|
|
WB Writeback_Exclusive_Dirty [764 ] 764
|
|
WB Pf_Replacement [0 ] 0
|
|
WB DMA_READ [0 ] 0
|
|
WB DMA_WRITE [0 ] 0
|
|
WB GETF [0 ] 0
|
|
|
|
WB_O_W GETX [0 ] 0
|
|
WB_O_W GETS [0 ] 0
|
|
WB_O_W PUT [0 ] 0
|
|
WB_O_W Pf_Replacement [0 ] 0
|
|
WB_O_W DMA_READ [0 ] 0
|
|
WB_O_W DMA_WRITE [0 ] 0
|
|
WB_O_W Memory_Ack [0 ] 0
|
|
WB_O_W GETF [0 ] 0
|
|
|
|
WB_E_W GETX [0 ] 0
|
|
WB_E_W GETS [0 ] 0
|
|
WB_E_W PUT [0 ] 0
|
|
WB_E_W Pf_Replacement [0 ] 0
|
|
WB_E_W DMA_READ [0 ] 0
|
|
WB_E_W DMA_WRITE [0 ] 0
|
|
WB_E_W Memory_Ack [763 ] 763
|
|
WB_E_W GETF [0 ] 0
|
|
|
|
NO_F GETX [0 ] 0
|
|
NO_F GETS [0 ] 0
|
|
NO_F PUT [0 ] 0
|
|
NO_F UnblockM [0 ] 0
|
|
NO_F Pf_Replacement [0 ] 0
|
|
NO_F GETF [0 ] 0
|
|
NO_F PUTF [0 ] 0
|
|
|
|
NO_F_W GETX [0 ] 0
|
|
NO_F_W GETS [0 ] 0
|
|
NO_F_W PUT [0 ] 0
|
|
NO_F_W Pf_Replacement [0 ] 0
|
|
NO_F_W DMA_READ [0 ] 0
|
|
NO_F_W DMA_WRITE [0 ] 0
|
|
NO_F_W Memory_Data [0 ] 0
|
|
NO_F_W GETF [0 ] 0
|
|
|