Andreas Hansson 2208ea049f MEM: Make the bus bridge unidirectional and fixed address range ... This patch makes the bus bridge uni-directional and specialises the bus ports to be a master port and a slave port. This greatly simplifies the assumptions on both sides as either port only has to deal with requests or responses. The following patches introduce the notion of master and slave ports, and would not be possible without this split of responsibilities. In making the bridge unidirectional, the address range mechanism of the bridge is also changed. For the cases where communication is taking place both ways, an additional bridge is needed. This causes issues with the existing mechanism, as the busses cannot determine when to stop iterating the address updates from the two bridges. To avoid this issue, and also greatly simplify the specification, the bridge now has a fixed set of address ranges, specified at creation time.		2012-01-17 12:55:09 -06:00
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configs	MEM: Make the bus bridge unidirectional and fixed address range	2012-01-17 12:55:09 -06:00
long	stats: undo parser change from initparam change	2012-01-16 22:37:05 -05:00
quick	Ruby: Change the access permissions for MOESI hammer	2012-01-17 12:55:07 -06:00
test-progs/hello	test: Hello world test program for Power	2009-10-27 09:24:40 -07:00
diff-out	diff-out: clean up options	2010-09-21 23:07:34 -07:00
halt.sh	Rearrange the FS configs to be more shared. Also check in the full-system tests. Reference stats coming soon.	2006-07-21 15:56:35 -04:00
run.py	sim: make Python Root object a singleton	2010-08-17 05:06:22 -07:00
SConscript	tests: fix spurious scons "Error 1" messages	2011-10-22 16:52:07 -07:00