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Brandon Potter 43418e7f81 syscall-emul: Move memState into its own file 
The Process class is full of implementation details and
structures related to SE Mode. This changeset factors out an
internal class from Process and moves it into a separate file.
The purpose behind doing this is to clean up the code and make
it a bit more modular.

Change-Id: Ic6941a1657751e8d51d5b6b1dcc04f1195884280
Reviewed-on: https://gem5-review.googlesource.com/2263
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-03-09 19:19:38 +00:00
..
insts style: [patch 1/22] use /r/3648/ to reorganize includes 2016-11-09 14:27:37 -06:00
isa syscall_emul: [patch 13/22] add system call retry capability 2015-07-20 09:15:21 -05:00
linux syscall_emul: [patch 5/22] remove LiveProcess class and use Process instead 2016-11-09 14:27:40 -06:00
decoder.cc ISA,CPU: Generalize and split out the components of the decode cache. 2012-05-26 13:45:12 -07:00
decoder.hh isa: Add parameter to pick different decoder inside ISA 2015-10-09 14:50:54 -05:00
faults.hh Faults: Replace calls to genMachineCheckFault with M5PanicFault. 2011-09-27 00:24:43 -07:00
interrupts.cc SE/FS: Build the Interrupt objects in SE mode. 2011-10-09 00:15:50 -07:00
interrupts.hh style: [patch 3/22] reduce include dependencies in some headers 2016-11-09 14:27:40 -06:00
isa.cc style: [patch 1/22] use /r/3648/ to reorganize includes 2016-11-09 14:27:37 -06:00
isa.hh revert 5af8f40d8f2c 2015-07-28 01:58:04 -05:00
isa_traits.hh arch: Cleanup unused ISA traits constants 2014-09-03 07:42:21 -04:00
kernel_stats.hh Power: Add a stub kernel_stats.hh. 2011-11-13 12:40:15 -08:00
locked_mem.hh cpu: Add CPU support for generatig wake up events when LLSC adresses are snooped. 2014-01-24 15:29:30 -06:00
microcode_rom.hh Make commenting on close namespace brackets consistent. 2011-01-03 14:35:43 -08:00
miscregs.hh Make commenting on close namespace brackets consistent. 2011-01-03 14:35:43 -08:00
mmapped_ipr.hh arch: Add support for m5ops using mmapped IPRs 2013-09-30 12:20:43 +02:00
pagetable.cc style: [patch 1/22] use /r/3648/ to reorganize includes 2016-11-09 14:27:37 -06:00
pagetable.hh sim: Refactor the serialization base class 2015-07-07 09:51:03 +01:00
PowerInterrupts.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
PowerISA.py arch: Make the ISA class inherit from SimObject 2013-01-07 13:05:35 -05:00
PowerTLB.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
process.cc syscall-emul: Move memState into its own file 2017-03-09 19:19:38 +00:00
process.hh syscall_emul: [patch 5/22] remove LiveProcess class and use Process instead 2016-11-09 14:27:40 -06:00
pseudo_inst.hh kvm, x86: Adding support for SE mode execution 2014-11-23 18:01:08 -08:00
registers.hh revert 5af8f40d8f2c 2015-07-28 01:58:04 -05:00
remote_gdb.cc style: [patch 3/22] reduce include dependencies in some headers 2016-11-09 14:27:40 -06:00
remote_gdb.hh arm: remote GDB: rationalize structure of register offsets 2015-12-18 15:12:07 -06:00
SConscript style: remove trailing whitespace 2016-02-06 17:21:18 -08:00
SConsopts POWER: Add support for the Power ISA 2009-10-27 09:24:39 -07:00
stacktrace.cc style: [patch 1/22] use /r/3648/ to reorganize includes 2016-11-09 14:27:37 -06:00
stacktrace.hh arch: Use const StaticInstPtr references where possible 2014-09-27 09:08:36 -04:00
tlb.cc style: [patch 1/22] use /r/3648/ to reorganize includes 2016-11-09 14:27:37 -06:00
tlb.hh scons: Add missing override to appease clang 2016-02-23 03:27:20 -05:00
types.hh misc: Remove redundant compiler-specific defines 2015-10-12 04:07:59 -04:00
utility.cc style: [patch 1/22] use /r/3648/ to reorganize includes 2016-11-09 14:27:37 -06:00
utility.hh arch: Use const StaticInstPtr references where possible 2014-09-27 09:08:36 -04:00
vtophys.cc Implement Ali's review feedback. 2012-01-29 02:04:34 -08:00
vtophys.hh Merge with main repository. 2012-01-30 21:07:57 -08:00