b8a2d1e5c7
fixing things, partly by ignoring CPU models
that don't currently compile.
SConscript:
Split sources for fast, simple, and o3 CPU models into
separate source lists. For now none of these are included
in the base source list, so you won't get any CPU models
at all... but we still can't compile the other stuff so
it's not an issue.
Also get rid of obsolete encumbered/mem file.
base/loader/aout_object.cc:
base/loader/aout_object.hh:
base/loader/ecoff_object.cc:
base/loader/ecoff_object.hh:
base/loader/elf_object.cc:
base/loader/elf_object.hh:
base/loader/object_file.hh:
cpu/exec_context.cc:
sim/process.cc:
sim/system.cc:
sim/system.hh:
FunctionalMemory -> Memory
cpu/pc_event.hh:
Get rid of unused badpc.
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
Move Port functions into .cc file.
mem/port.hh:
Make recvAddressRangesQuery panic by default instead
of being abstract... do CPUs need to implement this?
mem/request.hh:
Add prefetch flags.
sim/syscall_emul.hh:
Start to fix...
--HG--
extra : convert_revision : ece53b3855f20916caaa381598ac37e8c7adfba7
108 lines
3.6 KiB
C++
108 lines
3.6 KiB
C++
/*
|
|
* Copyright (c) 2002-2005 The Regents of The University of Michigan
|
|
* All rights reserved.
|
|
*
|
|
* Redistribution and use in source and binary forms, with or without
|
|
* modification, are permitted provided that the following conditions are
|
|
* met: redistributions of source code must retain the above copyright
|
|
* notice, this list of conditions and the following disclaimer;
|
|
* redistributions in binary form must reproduce the above copyright
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
* documentation and/or other materials provided with the distribution;
|
|
* neither the name of the copyright holders nor the names of its
|
|
* contributors may be used to endorse or promote products derived from
|
|
* this software without specific prior written permission.
|
|
*
|
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
*/
|
|
|
|
/**
|
|
* @file Decleration of a request, the overall memory request consisting of
|
|
the parts of the request that are persistent throughout the transaction.
|
|
*/
|
|
|
|
#ifndef __MEM_REQUEST_HH__
|
|
#define __MEM_REQUEST_HH__
|
|
|
|
#include "targetarch/isa_traits.hh"
|
|
|
|
class Request;
|
|
class CpuRequest;
|
|
|
|
typedef Request* RequestPtr;
|
|
typedef CpuRequest* CpuRequestPtr;
|
|
|
|
/** The request is a Load locked/store conditional. */
|
|
const unsigned LOCKED = 0x001;
|
|
/** The virtual address is also the physical address. */
|
|
const unsigned PHYSICAL = 0x002;
|
|
/** The request is an ALPHA VPTE pal access (hw_ld). */
|
|
const unsigned VPTE = 0x004;
|
|
/** Use the alternate mode bits in ALPHA. */
|
|
const unsigned ALTMODE = 0x008;
|
|
/** The request is to an uncacheable address. */
|
|
const unsigned UNCACHEABLE = 0x010;
|
|
/** The request should not cause a page fault. */
|
|
const unsigned NO_FAULT = 0x020;
|
|
/** The request should be prefetched into the exclusive state. */
|
|
const unsigned PF_EXCLUSIVE = 0x100;
|
|
/** The request should be marked as LRU. */
|
|
const unsigned EVICT_NEXT = 0x200;
|
|
|
|
class Request
|
|
{
|
|
//@todo Make Accesor functions, make these private.
|
|
public:
|
|
/** The physical address of the request. */
|
|
Addr paddr;
|
|
|
|
/** whether this req came from the CPU or not **DO we need this??***/
|
|
bool nicReq;
|
|
|
|
/** The size of the request. */
|
|
int size;
|
|
|
|
/** The time this request was started. Used to calculate latencies. */
|
|
Tick time;
|
|
|
|
/** Destination address if this is a block copy. */
|
|
Addr copyDest;
|
|
|
|
uint32_t flags;
|
|
};
|
|
|
|
class CpuRequest : public Request
|
|
{
|
|
//@todo Make Accesor functions, make these private.
|
|
public:
|
|
/** The virtual address of the request. */
|
|
Addr vaddr;
|
|
|
|
/** The address space ID. */
|
|
int asid;
|
|
|
|
/** The return value of store conditional. */
|
|
uint64_t scResult;
|
|
|
|
/** The cpu number for statistics. */
|
|
int cpuNum;
|
|
|
|
/** The requesting thread id. */
|
|
int threadNum;
|
|
|
|
/** program counter of initiating access; for tracing/debugging */
|
|
Addr pc;
|
|
};
|
|
|
|
#endif // __MEM_REQUEST_HH__
|