b6247c9ea7
Ready to start testing if I could fix the linking errors I can't ever seem to fix. cpu/simple/cpu.cc: cpu/simple/cpu.hh: Add connecting of ports until builder can handle it. mem/physical.cc: Add function to allocate a port in the object Remove some full_sys stuff untill needed mem/physical.hh: Add function to allocate a port in the object python/m5/objects/BaseCPU.py: Update the params sim/process.cc: Make sure to use the right name (hopefully CPU constructor already called) --HG-- extra : convert_revision : 4089caf20d7eb53e5463c8ac93ddce5e43ea5d85 |
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bus.hh | ||
mem_object.hh | ||
packet.hh | ||
page_table.cc | ||
page_table.hh | ||
physical.cc | ||
physical.hh | ||
port.cc | ||
port.hh | ||
request.hh | ||
translating_port.cc | ||
translating_port.hh |