13a15c55a4
Coherence protocol change basically got rid of UpgradeReqs in L2 caches, other minor related cache stat changes.
46 lines
1.5 KiB
Text
Executable file
46 lines
1.5 KiB
Text
Executable file
M5 Simulator System
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Copyright (c) 2001-2008
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The Regents of The University of Michigan
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All Rights Reserved
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M5 compiled Sep 20 2010 15:04:50
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M5 revision 0c4a7d867247 7686 default qtip print-identical tip
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M5 started Sep 20 2010 15:05:18
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M5 executing on phenom
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command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing
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Global frequency set at 1000000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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spec_init
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Loading Input Data
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Duplicating 262144 bytes
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Duplicating 524288 bytes
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Input data 1048576 bytes in length
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Compressing Input Data, level 1
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Compressed data 108074 bytes in length
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Uncompressing Data
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Uncompressed data 1048576 bytes in length
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Uncompressed data compared correctly
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Compressing Input Data, level 3
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Compressed data 97831 bytes in length
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Uncompressing Data
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Uncompressed data 1048576 bytes in length
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Uncompressed data compared correctly
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Compressing Input Data, level 5
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Compressed data 83382 bytes in length
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Uncompressing Data
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Uncompressed data 1048576 bytes in length
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Uncompressed data compared correctly
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Compressing Input Data, level 7
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Compressed data 76606 bytes in length
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Uncompressing Data
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Uncompressed data 1048576 bytes in length
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Uncompressed data compared correctly
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Compressing Input Data, level 9
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Compressed data 73189 bytes in length
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Uncompressing Data
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Uncompressed data 1048576 bytes in length
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Uncompressed data compared correctly
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Tested 1MB buffer: OK!
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Exiting @ tick 796759936000 because target called exit()
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