sanchayanmaity/gem5
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4 commits

Author SHA1 Message Date
Steve Reinhardt
13a15c55a4 stats: update stats for previous cset 
Coherence protocol change basically got rid
of UpgradeReqs in L2 caches, other minor
related cache stat changes.
 2010-09-21 23:07:35 -07:00
Steve Reinhardt
9e45ada171 stats: update stats for preceding coherence changes 
Because the handling of the E state for multilevel caches
has changed, stats are affected for any non-ruby config
with caches, even uniprocessor simple CPU.
 2010-09-09 14:40:19 -04:00
Ali Saidi
e6d3fe8a0c ARM: Update regression tests for ldr/str microcode changes. 2010-08-25 19:10:42 -05:00
Ali Saidi
1b73376b0b ARM: Add regression tests 2010-07-27 01:03:44 -04:00