b25ea094d4
The current TLM bridge only provides a Slave Port that allows the gem5 world to send request to the SystemC world. This patch series refractors and cleans up the existing code, and adds a Master Port that allows the SystemC world to send requests to the gem5 world. This patch: * Restructure the existing sources in preparation of the addition of the * new Master Port. * Refractor names to allow for distinction of the slave and master port. * Replace the Makefile by a SConstruct. Testing Done: The examples provided in util/tlm (now util/tlm/examples/slave_port) still compile and run error free. Reviewed at http://reviews.gem5.org/r/3527/ Signed-off-by: Jason Lowe-Power <jason@lowepower.com> |
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.. | ||
__init__.py | ||
Benchmarks.py | ||
CacheConfig.py | ||
Caches.py | ||
cpu2000.py | ||
CpuConfig.py | ||
FSConfig.py | ||
GPUTLBConfig.py | ||
GPUTLBOptions.py | ||
HMC.py | ||
MemConfig.py | ||
O3_ARM_v7a.py | ||
Options.py | ||
PlatformConfig.py | ||
SimpleOpts.py | ||
Simulation.py | ||
SysPaths.py |