gem5/src/cpu/o3/alpha
Nathan Binkert abc76f20cb Major changes to how SimObjects are created and initialized. Almost all
creation and initialization now happens in python.  Parameter objects
are generated and initialized by python.  The .ini file is now solely for
debugging purposes and is not used in construction of the objects in any
way.

--HG--
extra : convert_revision : 7e722873e417cb3d696f2e34c35ff488b7bff4ed
2007-07-23 21:51:38 -07:00
..
cpu.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
cpu.hh *MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg 2007-03-07 15:04:31 -05:00
cpu_builder.cc Major changes to how SimObjects are created and initialized. Almost all 2007-07-23 21:51:38 -07:00
cpu_impl.hh Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU functions. 2007-04-04 15:38:59 -04:00
dyn_inst.cc Make O3CPU model independent of the ISA 2006-06-30 19:52:08 -04:00
dyn_inst.hh Add extra constructors to Alpha and MIPS 2007-04-15 21:51:05 +00:00
dyn_inst_impl.hh Add extra constructors to Alpha and MIPS 2007-04-15 21:51:05 +00:00
impl.hh more steps toward O3 SMT 2006-07-06 11:25:44 -04:00
params.hh Adjustments for the AlphaTLB changing to AlphaISA::TLB and changing register file functions to not take faults 2006-11-01 16:44:45 -05:00
thread_context.cc Make O3CPU model independent of the ISA 2006-06-30 19:52:08 -04:00
thread_context.hh Implement a stub nnpc for alpha that is read only as npc+4. 2006-12-28 14:27:45 -05:00