Nilay Vaish aafa5c3f86 revert 5af8f40d8f2c		2015-07-28 01:58:04 -05:00
..
probes	cpu: commit probe notification on every microop or macroop	2015-01-20 14:15:27 -06:00
atomic.cc	sim: Refactor and simplify the drain API	2015-07-07 09:51:05 +01:00
atomic.hh	sim: Refactor and simplify the drain API	2015-07-07 09:51:05 +01:00
AtomicSimpleCPU.py	cpu: use probes infrastructure to do simpoint profiling	2014-09-20 17:17:43 -04:00
base.cc	sim: Refactor the serialization base class	2015-07-07 09:51:03 +01:00
base.hh	revert 5af8f40d8f2c	2015-07-28 01:58:04 -05:00
BaseSimpleCPU.py	cpu: re-organizes the branch predictor structure.	2015-04-13 17:33:57 -05:00
SConscript	scons: rename TraceFlags to DebugFlags	2011-06-02 17:36:21 -07:00
SConsopts	arch, cpu: Factor out the ExecContext into a proper base class	2014-09-03 07:42:22 -04:00
timing.cc	sim: Refactor and simplify the drain API	2015-07-07 09:51:05 +01:00
timing.hh	sim: Refactor and simplify the drain API	2015-07-07 09:51:05 +01:00
TimingSimpleCPU.py	cpu: Add CPU metadata om the Python classes	2013-02-15 17:40:08 -05:00