Gabe Black a6757095c3 Add in support for condition code flags. ... Some microops can set the condition codes, and some of them can be predicated on them. Some of the codes aren't implemented because it was unclear from the AMD patent what they actually did. They are used with string instructions, but they use variables IP, DTF, and SSTF which don't appear to be documented. --HG-- extra : convert_revision : 2236cccd07d0091762b50148975f301bb1d2da3f		2007-07-17 15:33:18 -07:00
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alpha	Make branches work by repopulating the predecoder every time through. This is probably fine as far as the predecoder goes, but the simple cpu might want to not refetch something it already has. That reintroduces the self modifying code problem though.	2007-06-19 18:17:34 +00:00
mips	fix store instructions, pass fast/quick Atomic/TimingSimpleCPU regressions...	2007-06-29 15:13:50 -04:00
sparc	Merge zizzer.eecs.umich.edu:/bk/newmem	2007-06-21 20:35:25 +00:00
x86	Add in support for condition code flags.	2007-07-17 15:33:18 -07:00
isa_parser.py	FINISH off merge of mips mt/dsp isa extensions by adding the ControlBitfieldOPerand to ISA Parser. Now, while things do build, we have to fix broken functionality...	2007-06-22 21:09:35 -04:00
isa_specific.hh	Add build hooks for x86.	2007-03-03 16:01:48 +00:00
micro_asm.py	Fix a problem where part of a microops parameters might be interpretted as an "ID", and also added support for symbols.	2007-06-21 15:26:01 +00:00
micro_asm_test.py	Add a second section to make sure the ROM is extended properly.	2007-05-31 22:21:21 +00:00
SConscript	Merge zizzer.eecs.umich.edu:/bk/newmem	2007-03-15 02:52:51 +00:00