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Andreas Hansson 995e6e4670 Bus: Add a notion of layers to the buses 
This patch moves all flow control, arbitration and state information
into a bus layer. The layer is thus responsible for all the state
transitions, and for keeping hold of the retry list. Consequently the
layer is also responsible for the draining.

With this change, the non-coherent and coherent bus are given a single
layer to avoid changing any temporal behaviour, but the patch opens up
for adding more layers.
2012-07-09 12:35:36 -04:00
build_opts Regression: Add a test for x86 timing full system ruby simulation 2012-04-25 22:43:36 -05:00
configs configs: add run scripts for ics/gb versions of android and bbench 2012-06-11 11:07:42 -04:00
ext clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6 2012-04-14 05:43:31 -04:00
src Bus: Add a notion of layers to the buses 2012-07-09 12:35:36 -04:00
system ARM: Add support for Versatile Express extended memory map 2012-03-01 17:26:31 -06:00
tests Stats: Update stats for RAS and LRU fixes. 2012-06-29 11:19:03 -04:00
util Style: Make style.py's invalid warning print which file caused the infraction. 2012-06-29 11:19:06 -04:00
.hgignore .hgignore: added src/doxygen 2010-07-27 20:00:38 -07:00
.hgtags Added tag Calvin_Submission for changeset 5de565c4b7bd 2009-11-18 11:55:42 -06:00
COPYING copyright: Add code for finding all copyright blocks and create a COPYING file 2011-06-02 17:36:07 -07:00
LICENSE copyright: Add code for finding all copyright blocks and create a COPYING file 2011-06-02 17:36:07 -07:00
README Info: Clean up some info files. 2011-02-14 21:36:37 -08:00
SConstruct swig: Use SWIG from environment when determining version 2012-06-20 19:32:42 -04:00

README 

This is the M5 simulator.

For detailed information about building the simulator and getting
started please refer to http://www.m5sim.org.

Specific pages of interest are:
http://www.m5sim.org/wiki/index.php/Compiling_M5
http://www.m5sim.org/wiki/index.php/Running_M5

Short version:

1. If you don't have SCons version 0.98.1 or newer, get it from
http://wwww.scons.org.

2. If you don't have SWIG version 1.3.31 or newer, get it from
http://wwww.swig.org.

3. Make sure you also have gcc version 3.4.6 or newer, Python 2.4 or newer
(the dev version with header files), zlib, and the m4 preprocessor.

4. In this directory, type 'scons build/ALPHA_SE/tests/debug/quick'.  This
will build the debug version of the m5 binary (m5.debug) for the Alpha
syscall emulation target, and run the quick regression tests on it.

If you have questions, please send mail to m5-users@m5sim.org

WHAT'S INCLUDED (AND NOT)
-------------------------

The basic source release includes these subdirectories:
 - m5:
   - configs: simulation configuration scripts
   - ext: less-common external packages needed to build m5
   - src: source code of the m5 simulator
   - system: source for some optional system software for simulated systems
   - tests: regression tests
   - util: useful utility programs and files

To run full-system simulations, you will need compiled system firmware
(console and PALcode for Alpha), kernel binaries and one or more disk images. 
These files for Alpha are collected in a separate archive, m5_system.tar.bz2.
This file can he downloaded separately.

Depending on the ISA used, M5 may support Linux 2.4/2.6, FreeBSD, and the
proprietary Compaq/HP Tru64 version of Unix. We are able to distribute Linux
and FreeBSD bootdisks, but we are unable to distribute bootable disk images of
Tru64 Unix. If you have a Tru64 license and are interested in
obtaining disk images, contact us at m5-users@m5sim.org