gem5/src/arch
Korey Sewell 738ecc495b fix store instructions, pass fast/quick Atomic/TimingSimpleCPU regressions...
src/arch/mips/isa/decoder.isa:
    commment out deret instruction for now...
src/arch/mips/isa/formats/fp.isa:
    edit fp format
src/arch/mips/isa/formats/mem.isa:
    fix for basic store instructions

--HG--
extra : convert_revision : 30cb5a474e78ac9292b6ab37d433db947a177731
2007-06-29 15:13:50 -04:00
..
alpha Make branches work by repopulating the predecoder every time through. This is probably fine as far as the predecoder goes, but the simple cpu might want to not refetch something it already has. That reintroduces the self modifying code problem though. 2007-06-19 18:17:34 +00:00
mips fix store instructions, pass fast/quick Atomic/TimingSimpleCPU regressions... 2007-06-29 15:13:50 -04:00
sparc Merge zizzer.eecs.umich.edu:/bk/newmem 2007-06-21 20:35:25 +00:00
x86 Make symbols for regular registers. 2007-06-21 20:35:27 +00:00
isa_parser.py FINISH off merge of mips mt/dsp isa extensions by adding the ControlBitfieldOPerand to ISA Parser. Now, while things do build, we have to fix broken functionality... 2007-06-22 21:09:35 -04:00
isa_specific.hh Add build hooks for x86. 2007-03-03 16:01:48 +00:00
micro_asm.py Fix a problem where part of a microops parameters might be interpretted as an "ID", and also added support for symbols. 2007-06-21 15:26:01 +00:00
micro_asm_test.py Add a second section to make sure the ROM is extended properly. 2007-05-31 22:21:21 +00:00
SConscript Merge zizzer.eecs.umich.edu:/bk/newmem 2007-03-15 02:52:51 +00:00