8e9d44477c
dev/sinic.cc: - Size the virtualRegs array based on the configured value - Add debugging stuff for uniquely identifying vnic usage - Only count totally unprocessed packets when notifying via RxDone - Add initial virtual address support - Fix some bugs in accessing packets out of order to make sure that busy packets are processed first - Add fifo watermark stuff - Make number of vnics, zero/delay copy and watermarks parameters dev/sinic.hh: add rxUnique and txUnique to uniquely identify tx and rx VNICs Create a separate list of Busy VNICs since more than one might be busy and we want to service those first Add more watermark stuff and new parameters dev/sinicreg.hh: Make the number of virtual nics a read-only parameter add bits for ZeroCopy/DelayCopy rename Virtual to Vaddr so it's not ambiguous Add a flag for TxData/RxData to indicate a virtual address Report rxfifo status in RxDone python/m5/objects/Ethernet.py: add more options for the fifo thresholds add number of vnics as a parameter add copy type as a parameter add virtual addressing as a parameter --HG-- extra : convert_revision : 850e2433b585d65469d4c5d85ad7ca820db10f4a |
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.. | ||
AlphaConsole.py | ||
AlphaFullCPU.py | ||
AlphaTLB.py | ||
BadDevice.py | ||
BaseCache.py | ||
BaseCPU.py | ||
Bus.py | ||
CoherenceProtocol.py | ||
Device.py | ||
DiskImage.py | ||
Ethernet.py | ||
Ide.py | ||
IntrControl.py | ||
MemTest.py | ||
Pci.py | ||
PhysicalMemory.py | ||
Platform.py | ||
Process.py | ||
Repl.py | ||
Root.py | ||
SimConsole.py | ||
SimpleDisk.py | ||
System.py | ||
Tsunami.py | ||
Uart.py |