Eric Van Hensbergen 7630168a75 arm: m5ops readfile64 args broken, offset coming through garbage ... There were several sections of the m5ops code which were essentially copy/pasted versions of the 32-bit code. The problem is that some of these didn't account fo4 64-bit registers leading to arguments being in the wrong registers. This patch addresses the args for readfile64, writefile64, and addsymbol64 -- all of which seemed to suffer from a similar set of problems when moving to 64-bit.		2014-03-23 11:11:34 -04:00
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alpha	alpha: Small removal of dead comments/code from alpha ISA	2014-03-12 07:03:22 -05:00
arm	arm: m5ops readfile64 args broken, offset coming through garbage	2014-03-23 11:11:34 -04:00
generic	mem: Remove explict cast from memhelper.	2014-01-24 15:29:30 -06:00
mips	cpu: Enable fast-forwarding for MIPS InOrderCPU and O3CPU	2014-03-01 23:35:23 -06:00
null	mem: Wakeup sleeping CPUs without caches on LLSC	2014-03-07 15:56:23 -05:00
power	arch: Make all register index flattening const	2014-01-24 15:29:30 -06:00
sparc	arch: Make all register index flattening const	2014-01-24 15:29:30 -06:00
x86	kvm: x86: Add support for x86 INIT and STARTUP handling	2014-03-16 17:28:23 +01:00
isa_parser.py	cpu: add a condition-code register class	2013-10-15 14:22:44 -04:00
micro_asm.py	scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access	2009-09-22 15:24:16 -07:00
micro_asm_test.py	Add a second section to make sure the ROM is extended properly.	2007-05-31 22:21:21 +00:00
SConscript	cpu: add a condition-code register class	2013-10-15 14:22:44 -04:00