Andreas Hansson 7c18691db1 mem: Rename SimpleDRAM to a more suitable DRAMCtrl ... This patch renames the not-so-simple SimpleDRAM to a more suitable DRAMCtrl. The name change is intended to ensure that we do not send the wrong message (although the "simple" in SimpleDRAM was originally intended as in cleverly simple, or elegant). As the DRAM controller modelling work is being presented at ISPASS'14 our hope is that a broader audience will use the model in the future. --HG-- rename : src/mem/SimpleDRAM.py => src/mem/DRAMCtrl.py rename : src/mem/simple_dram.cc => src/mem/dram_ctrl.cc rename : src/mem/simple_dram.hh => src/mem/dram_ctrl.hh		2014-03-23 11:12:12 -04:00
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Benchmarks.py	configs: add run scripts for ics/gb versions of android and bbench	2012-06-11 11:07:42 -04:00
CacheConfig.py	config: Update script to set cache line size on system	2013-07-18 08:31:19 -04:00
Caches.py	config: Update script to set cache line size on system	2013-07-18 08:31:19 -04:00
cpu2000.py	arm: Add support for ARMv8 (AArch64 & AArch32)	2014-01-24 15:29:34 -06:00
CpuConfig.py	config: Add a 'kvm' CPU alias	2013-09-30 09:45:43 +02:00
FSConfig.py	config: remove ruby_fs.py	2014-03-20 08:03:09 -05:00
MemConfig.py	mem: Rename SimpleDRAM to a more suitable DRAMCtrl	2014-03-23 11:12:12 -04:00
O3_ARM_v7a.py	arm: Add support for ARMv8 (AArch64 & AArch32)	2014-01-24 15:29:34 -06:00
Options.py	mem: Change memory defaults to be more representative	2014-03-23 11:12:10 -04:00
Simulation.py	config: Initialize and check cpt_starttick	2013-09-11 15:34:21 -05:00
SysPaths.py	make rcS files read from the m5 source directory, not /dist.	2006-11-08 14:10:25 -05:00