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cache
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Make L2+ caches allocate new block for writeback misses
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2008-02-16 14:58:03 -05:00 |
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config
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Backing in more changsets, getting closer to compile
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2006-06-28 14:35:00 -04:00 |
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bridge.cc
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Add functional PrintReq command for memory-system debugging.
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2008-01-02 12:20:15 -08:00 |
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bridge.hh
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Make the Event::description() a const function
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2008-02-06 16:32:40 -05:00 |
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Bridge.py
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DMA: Add IOCache and fix bus bridge to optionally only send requests one
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2007-08-10 16:14:01 -04:00 |
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bus.cc
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Bus: Fix the bus timing to be more realistic.
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2008-02-26 02:20:08 -05:00 |
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bus.hh
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Bus: Fix the bus timing to be more realistic.
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2008-02-26 02:20:08 -05:00 |
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Bus.py
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Bus: Fix the bus timing to be more realistic.
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2008-02-26 02:20:08 -05:00 |
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dram.cc
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Major changes to how SimObjects are created and initialized. Almost all
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2007-07-23 21:51:38 -07:00 |
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dram.hh
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Major changes to how SimObjects are created and initialized. Almost all
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2007-07-23 21:51:38 -07:00 |
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mem_object.cc
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params: Deprecate old-style constructors; update most SimObject constructors.
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2007-08-30 15:16:59 -04:00 |
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mem_object.hh
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params: Deprecate old-style constructors; update most SimObject constructors.
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2007-08-30 15:16:59 -04:00 |
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MemObject.py
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Major changes to how SimObjects are created and initialized. Almost all
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2007-07-23 21:51:38 -07:00 |
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packet.cc
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Add ReadRespWithInvalidate to handle multi-level coherence situation
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2008-01-02 15:22:38 -08:00 |
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packet.hh
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Add ReadRespWithInvalidate to handle multi-level coherence situation
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2008-01-02 15:22:38 -08:00 |
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packet_access.hh
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Make byteswap work correctly on Twin??_t types.
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2007-03-07 17:46:04 +00:00 |
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page_table.cc
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Checkpointing: Name SE page table entries better so that there isn't a problem if multiple workloads are being run at once.
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2007-11-14 23:42:08 -05:00 |
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page_table.hh
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TLB: Fix serialization issues with the tlb entries and make the page table store the process, not the system.
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2007-10-25 19:04:44 -07:00 |
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physical.cc
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Additional comments and helper functions for PrintReq.
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2008-01-02 13:46:22 -08:00 |
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physical.hh
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Memory: Cache the physical memory start and size so we don't need a dynamic cast on every access.
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2007-11-19 18:23:43 -05:00 |
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PhysicalMemory.py
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DRAM: Make latency parameters be Param.Latency instead of ints.
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2007-11-01 17:30:50 -04:00 |
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port.cc
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Add functional PrintReq command for memory-system debugging.
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2008-01-02 12:20:15 -08:00 |
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port.hh
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Add functional PrintReq command for memory-system debugging.
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2008-01-02 12:20:15 -08:00 |
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port_impl.hh
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Put the ProcessInfo and StackTrace objects into the ISA namespaces.
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2006-11-08 00:52:04 -05:00 |
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request.hh
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Add in files from merge-bare-iron, get them compiling in FS and SE mode
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2007-11-13 16:58:16 -05:00 |
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SConscript
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Traceflags: Add SCons function to created a traceflag instead of having one file with them all.
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2007-10-31 01:21:54 -04:00 |
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tport.cc
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MemorySystem: Fix the use of ?: to produce correct results.
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2007-08-12 19:43:54 -04:00 |
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tport.hh
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memory system: fix functional access bug.
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2007-07-29 20:17:03 -07:00 |
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translating_port.cc
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fix the translating ports so it can add a page on a fault
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2007-05-09 15:37:46 -04:00 |
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translating_port.hh
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fix the translating ports so it can add a page on a fault
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2007-05-09 15:37:46 -04:00 |
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vport.cc
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implement vtophys and 32bit gdb support
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2007-02-18 19:57:46 -05:00 |
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vport.hh
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implement vtophys and 32bit gdb support
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2007-02-18 19:57:46 -05:00 |
