gem5/src/arch/x86/isa/microops
Gabe Black efbff349a9 X86: Significantly filled out misc regs.
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extra : convert_revision : 4c53be6568134d65e57f5411df986fd9a89e82c9
2007-10-07 18:16:00 -07:00
..
base.isa X86: Move the fp microops to their own file with their own base classes in C++ and python. 2007-09-19 18:27:55 -07:00
fpop.isa X86: Fix the movfp microop. 2007-10-02 22:58:04 -07:00
ldstop.isa X86: Implement the ldst microop and put it in existing microcode where appropriate. 2007-10-02 22:08:09 -07:00
limmop.isa X86: Make disassembly use the final register index. Add bits to indicate whether or not register indexes should be "folded". 2007-07-30 13:23:33 -07:00
microops.isa X86: Move the fp microops to their own file with their own base classes in C++ and python. 2007-09-19 18:27:55 -07:00
regop.isa X86: Significantly filled out misc regs. 2007-10-07 18:16:00 -07:00
specop.isa Add a generateDisassembly function to the MicroFault StaticInst. 2007-07-18 16:09:35 -07:00