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cache
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style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs
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2008-09-10 14:26:15 -04:00 |
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config
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Backing in more changsets, getting closer to compile
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2006-06-28 14:35:00 -04:00 |
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bridge.cc
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When nesting if statements, use braces to avoid ambiguous else clauses.
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2008-09-26 08:18:57 -07:00 |
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bridge.hh
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Don't FastAlloc MSHRs since we don't allocate them on the fly.
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2008-03-24 01:08:02 -04:00 |
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Bridge.py
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DMA: Add IOCache and fix bus bridge to optionally only send requests one
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2007-08-10 16:14:01 -04:00 |
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bus.cc
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Add missing newlines to Bus DPRINTFs.
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2008-07-15 14:38:51 -04:00 |
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bus.hh
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Backed out changeset 94a7bb476fca: caused memory leak.
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2008-06-28 13:19:38 -04:00 |
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Bus.py
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Bus: Fix the bus timing to be more realistic.
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2008-02-26 02:20:08 -05:00 |
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dram.cc
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style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs
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2008-09-10 14:26:15 -04:00 |
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dram.hh
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Major changes to how SimObjects are created and initialized. Almost all
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2007-07-23 21:51:38 -07:00 |
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mem_object.cc
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params: Get rid of the remnants of the old style parameter configuration stuff.
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2008-08-11 12:22:17 -07:00 |
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mem_object.hh
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params: Get rid of the remnants of the old style parameter configuration stuff.
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2008-08-11 12:22:17 -07:00 |
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MemObject.py
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Major changes to how SimObjects are created and initialized. Almost all
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2007-07-23 21:51:38 -07:00 |
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packet.cc
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Use ReadResp instead of LoadLockedResp for LoadLockedReq responses.
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2008-07-15 14:38:51 -04:00 |
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packet.hh
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Use ReadResp instead of LoadLockedResp for LoadLockedReq responses.
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2008-07-15 14:38:51 -04:00 |
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packet_access.hh
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Make byteswap work correctly on Twin??_t types.
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2007-03-07 17:46:04 +00:00 |
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page_table.cc
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Checkpointing: Name SE page table entries better so that there isn't a problem if multiple workloads are being run at once.
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2007-11-14 23:42:08 -05:00 |
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page_table.hh
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TLB: Fix serialization issues with the tlb entries and make the page table store the process, not the system.
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2007-10-25 19:04:44 -07:00 |
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physical.cc
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physmem: Add a null option to physical memory so it doesn't store data.
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2008-06-15 21:39:29 -07:00 |
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physical.hh
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style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs
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2008-09-10 14:26:15 -04:00 |
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PhysicalMemory.py
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Make default PhysicalMemory latency slightly more realistic.
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2008-08-03 18:13:29 -04:00 |
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port.cc
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Backed out changeset 94a7bb476fca: caused memory leak.
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2008-06-28 13:19:38 -04:00 |
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port.hh
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Backed out changeset 94a7bb476fca: caused memory leak.
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2008-06-28 13:19:38 -04:00 |
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port_impl.hh
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Put the ProcessInfo and StackTrace objects into the ISA namespaces.
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2006-11-08 00:52:04 -05:00 |
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request.hh
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style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs
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2008-09-10 14:26:15 -04:00 |
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SConscript
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SCons: add comments to SConscript documenting bug workaround
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2008-04-10 15:38:10 -04:00 |
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tport.cc
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Get rid of bogus bus assertion.
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2008-06-13 01:33:49 -04:00 |
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tport.hh
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memory system: fix functional access bug.
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2007-07-29 20:17:03 -07:00 |
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translating_port.cc
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fix the translating ports so it can add a page on a fault
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2007-05-09 15:37:46 -04:00 |
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translating_port.hh
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fix the translating ports so it can add a page on a fault
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2007-05-09 15:37:46 -04:00 |
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vport.cc
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Remove delVirtPort() and make getVirtPort() only return cached version.
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2008-07-01 10:25:07 -04:00 |
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vport.hh
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implement vtophys and 32bit gdb support
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2007-02-18 19:57:46 -05:00 |
