761 lines
85 KiB
Text
761 lines
85 KiB
Text
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---------- Begin Simulation Statistics ----------
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host_inst_rate 115372 # Simulator instruction rate (inst/s)
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host_mem_usage 204236 # Number of bytes of host memory used
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host_seconds 0.11 # Real time elapsed on the host
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host_tick_rate 127463354 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 12773 # Number of instructions simulated
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sim_seconds 0.000014 # Number of seconds simulated
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sim_ticks 14139000 # Number of ticks simulated
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.BTBHits 916 # Number of BTB hits
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system.cpu.BPredUnit.BTBLookups 4600 # Number of BTB lookups
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system.cpu.BPredUnit.RASInCorrect 174 # Number of incorrect RAS predictions.
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system.cpu.BPredUnit.condIncorrect 1521 # Number of conditional branches incorrect
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system.cpu.BPredUnit.condPredicted 3069 # Number of conditional branches predicted
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system.cpu.BPredUnit.lookups 5341 # Number of BP lookups
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system.cpu.BPredUnit.usedRAS 654 # Number of times the RAS was used to get a target.
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system.cpu.commit.COM:branches::0 1051 # Number of branches committed
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system.cpu.commit.COM:branches::1 1051 # Number of branches committed
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system.cpu.commit.COM:branches::total 2102 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 132 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited::0 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:bw_limited::1 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:bw_limited::total 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle::samples 22158 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::mean 0.577985 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::stdev 1.311672 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::0 16375 73.90% 73.90% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::1 2877 12.98% 86.89% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::2 1274 5.75% 92.63% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::3 599 2.70% 95.34% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::4 362 1.63% 96.97% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::5 252 1.14% 98.11% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::6 188 0.85% 98.96% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::7 99 0.45% 99.40% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::8 132 0.60% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::total 22158 # Number of insts commited each cycle
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system.cpu.commit.COM:count::0 6404 # Number of instructions committed
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system.cpu.commit.COM:count::1 6403 # Number of instructions committed
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system.cpu.commit.COM:count::total 12807 # Number of instructions committed
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system.cpu.commit.COM:loads::0 1185 # Number of loads committed
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system.cpu.commit.COM:loads::1 1185 # Number of loads committed
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system.cpu.commit.COM:loads::total 2370 # Number of loads committed
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system.cpu.commit.COM:membars::0 0 # Number of memory barriers committed
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system.cpu.commit.COM:membars::1 0 # Number of memory barriers committed
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system.cpu.commit.COM:membars::total 0 # Number of memory barriers committed
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system.cpu.commit.COM:refs::0 2050 # Number of memory references committed
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system.cpu.commit.COM:refs::1 2050 # Number of memory references committed
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system.cpu.commit.COM:refs::total 4100 # Number of memory references committed
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system.cpu.commit.COM:swp_count::0 0 # Number of s/w prefetches committed
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system.cpu.commit.COM:swp_count::1 0 # Number of s/w prefetches committed
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system.cpu.commit.COM:swp_count::total 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 1116 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 12807 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 10253 # The number of squashed insts skipped by commit
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system.cpu.committedInsts::0 6387 # Number of Instructions Simulated
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system.cpu.committedInsts::1 6386 # Number of Instructions Simulated
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system.cpu.committedInsts_total 12773 # Number of Instructions Simulated
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system.cpu.cpi::0 4.427587 # CPI: Cycles Per Instruction
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system.cpu.cpi::1 4.428281 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 2.213967 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_accesses 3796 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency::0 36145.962733 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_miss_latency::total 36145.962733 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency::0 36908.415842 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 3474 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency::0 11639000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_latency::total 11639000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.084826 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 322 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits::0 120 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_hits::total 120 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency::0 7455500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_latency::total 7455500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.053214 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053214 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses::0 202 # number of ReadReq MSHR misses
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system.cpu.dcache.ReadReq_mshr_misses::total 202 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 1730 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency::0 32784.604520 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::total 32784.604520 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency::0 36119.863014 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 1022 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency::0 23211500 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::total 23211500 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.409249 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 708 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits::0 562 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_hits::total 562 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency::0 5273500 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_latency::total 5273500 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.084393 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses::0 146 # number of WriteReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 12.919540 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 5526 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency::0 33835.436893 # average overall miss latency
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system.cpu.dcache.demand_avg_miss_latency::1 0 # average overall miss latency
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system.cpu.dcache.demand_avg_miss_latency::total 33835.436893 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency::0 36577.586207 # average overall mshr miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency
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system.cpu.dcache.demand_hits 4496 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency::0 34850500 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_latency::total 34850500 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.186392 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 1030 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits::0 682 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_hits::total 682 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency::0 12729000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency::total 12729000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate::0 0.062975 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_miss_rate::total 0.062975 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses::0 348 # number of demand (read+write) MSHR misses
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system.cpu.dcache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses
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system.cpu.dcache.demand_mshr_misses::total 348 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events::0 0 # number of times MSHR cap was activated
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system.cpu.dcache.mshr_cap_events::1 0 # number of times MSHR cap was activated
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system.cpu.dcache.mshr_cap_events::total 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.occ_%::0 0.053836 # Average percentage of cache occupancy
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system.cpu.dcache.occ_blocks::0 220.510583 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses 5526 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency::0 33835.436893 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::1 0 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::total 33835.436893 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency::0 36577.586207 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 4496 # number of overall hits
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system.cpu.dcache.overall_miss_latency::0 34850500 # number of overall miss cycles
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system.cpu.dcache.overall_miss_latency::1 0 # number of overall miss cycles
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system.cpu.dcache.overall_miss_latency::total 34850500 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.186392 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 1030 # number of overall misses
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system.cpu.dcache.overall_mshr_hits::0 682 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_hits::1 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_hits::total 682 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency::0 12729000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::total 12729000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate::0 0.062975 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_miss_rate::total 0.062975 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses::0 348 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_misses::1 0 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_misses::total 348 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements::0 0 # number of replacements
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system.cpu.dcache.replacements::1 0 # number of replacements
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system.cpu.dcache.replacements::total 0 # number of replacements
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system.cpu.dcache.sampled_refs 348 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 220.510583 # Cycle average of tags in use
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system.cpu.dcache.total_refs 4496 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks::0 0 # number of writebacks
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system.cpu.dcache.writebacks::1 0 # number of writebacks
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system.cpu.dcache.writebacks::total 0 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 4667 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 414 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 569 # Number of times decode resolved a branch
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system.cpu.decode.DECODE:DecodedInsts 26624 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 32585 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 4771 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 2039 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:SquashedInsts 734 # Number of squashed instructions handled by decode
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system.cpu.decode.DECODE:UnblockCycles 167 # Number of cycles decode is unblocking
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system.cpu.dtb.data_accesses 6131 # DTB accesses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_hits 5993 # DTB hits
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system.cpu.dtb.data_misses 138 # DTB misses
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.read_accesses 3997 # DTB read accesses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_hits 3913 # DTB read hits
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system.cpu.dtb.read_misses 84 # DTB read misses
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system.cpu.dtb.write_accesses 2134 # DTB write accesses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_hits 2080 # DTB write hits
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system.cpu.dtb.write_misses 54 # DTB write misses
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system.cpu.fetch.Branches 5341 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 3993 # Number of cache lines fetched
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system.cpu.fetch.Cycles 9162 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 611 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 29881 # Number of instructions fetch has processed
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system.cpu.fetch.SquashCycles 1641 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.188868 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 3993 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 1570 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 1.056650 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist::samples 22205 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 1.345688 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.736511 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 17092 76.97% 76.97% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 418 1.88% 78.86% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 346 1.56% 80.41% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 428 1.93% 82.34% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 443 2.00% 84.34% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 320 1.44% 85.78% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 433 1.95% 87.73% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 283 1.27% 89.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 2442 11.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 22205 # Number of instructions fetched each cycle (Total)
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system.cpu.icache.ReadReq_accesses 3993 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency::0 35767.942584 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_miss_latency::total 35767.942584 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::0 35489.482201 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 3157 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency::0 29902000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 29902000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.209366 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_misses 836 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_mshr_hits::0 218 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 218 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::0 21932500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 21932500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::0 0.154771 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.154771 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_misses::0 618 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 618 # number of ReadReq MSHR misses
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_refs 5.108414 # Average number of references to valid blocks.
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.demand_accesses 3993 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_avg_miss_latency::0 35767.942584 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::1 0 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 35767.942584 # average overall miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::0 35489.482201 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency
|
|
system.cpu.icache.demand_hits 3157 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_miss_latency::0 29902000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 29902000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_rate 0.209366 # miss rate for demand accesses
|
|
system.cpu.icache.demand_misses 836 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_mshr_hits::0 218 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 218 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_miss_latency::0 21932500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 21932500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_rate::0 0.154771 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.154771 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_misses::0 618 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 618 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.mshr_cap_events::0 0 # number of times MSHR cap was activated
|
|
system.cpu.icache.mshr_cap_events::1 0 # number of times MSHR cap was activated
|
|
system.cpu.icache.mshr_cap_events::total 0 # number of times MSHR cap was activated
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.occ_%::0 0.155666 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_blocks::0 318.803897 # Average occupied blocks per context
|
|
system.cpu.icache.overall_accesses 3993 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_avg_miss_latency::0 35767.942584 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::1 0 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 35767.942584 # average overall miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::0 35489.482201 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency
|
|
system.cpu.icache.overall_hits 3157 # number of overall hits
|
|
system.cpu.icache.overall_miss_latency::0 29902000 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::1 0 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 29902000 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_rate 0.209366 # miss rate for overall accesses
|
|
system.cpu.icache.overall_misses 836 # number of overall misses
|
|
system.cpu.icache.overall_mshr_hits::0 218 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::1 0 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 218 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_miss_latency::0 21932500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 21932500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_rate::0 0.154771 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.154771 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_misses::0 618 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::1 0 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 618 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.icache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.icache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.icache.replacements::0 6 # number of replacements
|
|
system.cpu.icache.replacements::1 0 # number of replacements
|
|
system.cpu.icache.replacements::total 6 # number of replacements
|
|
system.cpu.icache.sampled_refs 618 # Sample count of references to valid blocks.
|
|
system.cpu.icache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.icache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.icache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.icache.tagsinuse 318.803897 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 3157 # Total number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.writebacks::0 0 # number of writebacks
|
|
system.cpu.icache.writebacks::1 0 # number of writebacks
|
|
system.cpu.icache.writebacks::total 0 # number of writebacks
|
|
system.cpu.idleCycles 6074 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.iew.EXEC:branches::0 1552 # Number of branches executed
|
|
system.cpu.iew.EXEC:branches::1 1552 # Number of branches executed
|
|
system.cpu.iew.EXEC:branches::total 3104 # Number of branches executed
|
|
system.cpu.iew.EXEC:nop::0 64 # number of nop insts executed
|
|
system.cpu.iew.EXEC:nop::1 70 # number of nop insts executed
|
|
system.cpu.iew.EXEC:nop::total 134 # number of nop insts executed
|
|
system.cpu.iew.EXEC:rate 0.666325 # Inst execution rate
|
|
system.cpu.iew.EXEC:refs::0 3105 # number of memory reference insts executed
|
|
system.cpu.iew.EXEC:refs::1 3045 # number of memory reference insts executed
|
|
system.cpu.iew.EXEC:refs::total 6150 # number of memory reference insts executed
|
|
system.cpu.iew.EXEC:stores::0 1087 # Number of stores executed
|
|
system.cpu.iew.EXEC:stores::1 1064 # Number of stores executed
|
|
system.cpu.iew.EXEC:stores::total 2151 # Number of stores executed
|
|
system.cpu.iew.EXEC:swp::0 0 # number of swp insts executed
|
|
system.cpu.iew.EXEC:swp::1 0 # number of swp insts executed
|
|
system.cpu.iew.EXEC:swp::total 0 # number of swp insts executed
|
|
system.cpu.iew.WB:consumers::0 5852 # num instructions consuming a value
|
|
system.cpu.iew.WB:consumers::1 5867 # num instructions consuming a value
|
|
system.cpu.iew.WB:consumers::total 11719 # num instructions consuming a value
|
|
system.cpu.iew.WB:count::0 9073 # cumulative count of insts written-back
|
|
system.cpu.iew.WB:count::1 9067 # cumulative count of insts written-back
|
|
system.cpu.iew.WB:count::total 18140 # cumulative count of insts written-back
|
|
system.cpu.iew.WB:fanout::0 0.775290 # average fanout of values written-back
|
|
system.cpu.iew.WB:fanout::1 0.774501 # average fanout of values written-back
|
|
system.cpu.iew.WB:fanout::total 1.549792 # average fanout of values written-back
|
|
system.cpu.iew.WB:penalized::0 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.WB:penalized::1 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.WB:penalized::total 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.WB:penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.iew.WB:penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.iew.WB:penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.iew.WB:producers::0 4537 # num instructions producing a value
|
|
system.cpu.iew.WB:producers::1 4544 # num instructions producing a value
|
|
system.cpu.iew.WB:producers::total 9081 # num instructions producing a value
|
|
system.cpu.iew.WB:rate::0 0.320839 # insts written-back per cycle
|
|
system.cpu.iew.WB:rate::1 0.320627 # insts written-back per cycle
|
|
system.cpu.iew.WB:rate::total 0.641465 # insts written-back per cycle
|
|
system.cpu.iew.WB:sent::0 9197 # cumulative count of insts sent to commit
|
|
system.cpu.iew.WB:sent::1 9165 # cumulative count of insts sent to commit
|
|
system.cpu.iew.WB:sent::total 18362 # cumulative count of insts sent to commit
|
|
system.cpu.iew.branchMispredicts 1270 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewBlockCycles 840 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewDispLoadInsts 4751 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 46 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewDispSquashedInsts 669 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispStoreInsts 2526 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispatchedInsts 23137 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewExecLoadInsts::0 2018 # Number of load instructions executed
|
|
system.cpu.iew.iewExecLoadInsts::1 1981 # Number of load instructions executed
|
|
system.cpu.iew.iewExecLoadInsts::total 3999 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 1059 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.iewExecutedInsts 18843 # Number of executed instructions
|
|
system.cpu.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.iewSquashCycles 2039 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewUnblockCycles 64 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.lsq.thread.0.forwLoads 57 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 68 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 1198 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread.0.squashedStores 429 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread.1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.lsq.thread.1.forwLoads 58 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread.1.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.1.memOrderViolation 63 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread.1.squashedLoads 1183 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread.1.squashedStores 367 # Number of stores squashed
|
|
system.cpu.iew.memOrderViolationEvents 131 # Number of memory order violations
|
|
system.cpu.iew.predictedNotTakenIncorrect 1010 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.predictedTakenIncorrect 260 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.ipc::0 0.225857 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc::1 0.225821 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.451678 # IPC: Total IPC of All Threads
|
|
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::IntAlu 6654 67.06% 67.08% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.01% 67.09% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.09% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 67.11% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.11% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.11% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.11% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.11% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.11% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.11% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.11% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.11% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.11% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.11% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.11% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.11% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.11% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.11% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.11% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.11% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.11% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.11% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.11% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.11% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.11% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 67.11% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.11% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.11% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.11% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::MemRead 2121 21.37% 88.48% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::MemWrite 1143 11.52% 100.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::total 9923 # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::IntAlu 6748 67.62% 67.64% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::IntMult 1 0.01% 67.65% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::IntDiv 0 0.00% 67.65% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::FloatAdd 2 0.02% 67.67% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::FloatCmp 0 0.00% 67.67% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::FloatCvt 0 0.00% 67.67% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::FloatMult 0 0.00% 67.67% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::FloatDiv 0 0.00% 67.67% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::FloatSqrt 0 0.00% 67.67% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::SimdAdd 0 0.00% 67.67% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::SimdAddAcc 0 0.00% 67.67% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::SimdAlu 0 0.00% 67.67% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::SimdCmp 0 0.00% 67.67% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::SimdCvt 0 0.00% 67.67% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::SimdMisc 0 0.00% 67.67% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::SimdMult 0 0.00% 67.67% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::SimdMultAcc 0 0.00% 67.67% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::SimdShift 0 0.00% 67.67% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::SimdShiftAcc 0 0.00% 67.67% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::SimdSqrt 0 0.00% 67.67% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::SimdFloatAdd 0 0.00% 67.67% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::SimdFloatAlu 0 0.00% 67.67% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::SimdFloatCmp 0 0.00% 67.67% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::SimdFloatCvt 0 0.00% 67.67% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::SimdFloatDiv 0 0.00% 67.67% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::SimdFloatMisc 0 0.00% 67.67% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::SimdFloatMult 0 0.00% 67.67% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::SimdFloatMultAcc 0 0.00% 67.67% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::SimdFloatSqrt 0 0.00% 67.67% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::MemRead 2103 21.07% 88.75% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::MemWrite 1123 11.25% 100.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::total 9979 # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::IntAlu 13402 67.34% 67.36% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::IntMult 2 0.01% 67.37% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::IntDiv 0 0.00% 67.37% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::FloatAdd 4 0.02% 67.39% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::FloatCmp 0 0.00% 67.39% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::FloatCvt 0 0.00% 67.39% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::FloatMult 0 0.00% 67.39% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::FloatDiv 0 0.00% 67.39% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::FloatSqrt 0 0.00% 67.39% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::SimdAdd 0 0.00% 67.39% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::SimdAddAcc 0 0.00% 67.39% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::SimdAlu 0 0.00% 67.39% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::SimdCmp 0 0.00% 67.39% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::SimdCvt 0 0.00% 67.39% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::SimdMisc 0 0.00% 67.39% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::SimdMult 0 0.00% 67.39% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::SimdMultAcc 0 0.00% 67.39% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::SimdShift 0 0.00% 67.39% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::SimdShiftAcc 0 0.00% 67.39% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::SimdSqrt 0 0.00% 67.39% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::SimdFloatAdd 0 0.00% 67.39% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::SimdFloatAlu 0 0.00% 67.39% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::SimdFloatCmp 0 0.00% 67.39% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::SimdFloatCvt 0 0.00% 67.39% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::SimdFloatDiv 0 0.00% 67.39% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::SimdFloatMisc 0 0.00% 67.39% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::SimdFloatMult 0 0.00% 67.39% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::SimdFloatMultAcc 0 0.00% 67.39% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::SimdFloatSqrt 0 0.00% 67.39% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::MemRead 4224 21.22% 88.61% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::MemWrite 2266 11.39% 100.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::total 19902 # Type of FU issued
|
|
system.cpu.iq.ISSUE:fu_busy_cnt::0 80 # FU busy when requested
|
|
system.cpu.iq.ISSUE:fu_busy_cnt::1 85 # FU busy when requested
|
|
system.cpu.iq.ISSUE:fu_busy_cnt::total 165 # FU busy when requested
|
|
system.cpu.iq.ISSUE:fu_busy_rate::0 0.004020 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.ISSUE:fu_busy_rate::1 0.004271 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.ISSUE:fu_busy_rate::total 0.008291 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::IntAlu 16 9.70% 9.70% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 9.70% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 9.70% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 9.70% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 9.70% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 9.70% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 9.70% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 9.70% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 9.70% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 9.70% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 9.70% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 9.70% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 9.70% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 9.70% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 9.70% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 9.70% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 9.70% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 9.70% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 9.70% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 9.70% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 9.70% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 9.70% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 9.70% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 9.70% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 9.70% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 9.70% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 9.70% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 9.70% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 9.70% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::MemRead 89 53.94% 63.64% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::MemWrite 60 36.36% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:issued_per_cycle::samples 22205 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.896285 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.439530 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::0 13672 61.57% 61.57% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::1 3186 14.35% 75.92% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::2 2211 9.96% 85.88% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::3 1439 6.48% 92.36% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::4 897 4.04% 96.40% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::5 509 2.29% 98.69% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::6 214 0.96% 99.65% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::7 56 0.25% 99.91% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::8 21 0.09% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::total 22205 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:rate 0.703773 # Inst issue rate
|
|
system.cpu.iq.iqInstsAdded 22957 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqInstsIssued 19902 # Number of instructions issued
|
|
system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqSquashedInstsExamined 9000 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedInstsIssued 75 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.iqSquashedOperandsExamined 5071 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.fetch_accesses 4049 # ITB accesses
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
system.cpu.itb.fetch_hits 3993 # ITB hits
|
|
system.cpu.itb.fetch_misses 56 # ITB misses
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.l2cache.ReadExReq_accesses 146 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::0 34643.835616 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34643.835616 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::0 31544.520548 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_miss_latency::0 5058000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 5058000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_misses 146 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::0 4605500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4605500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::0 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::0 146 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_accesses 820 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::0 34537.897311 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34537.897311 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::0 31396.088020 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_miss_latency::0 28252000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 28252000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.997561 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_misses 818 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::0 25682000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25682000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::0 0.997561 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997561 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::0 818 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 818 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6750 # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_refs 0.002445 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 27000 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.demand_accesses 966 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_avg_miss_latency::0 34553.941909 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::1 0 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 34553.941909 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::0 31418.568465 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_miss_latency::0 33310000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 33310000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_rate 0.997930 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_misses 964 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_mshr_hits::0 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_miss_latency::0 30287500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 30287500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_rate::0 0.997930 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.997930 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_misses::0 964 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 964 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.mshr_cap_events::0 0 # number of times MSHR cap was activated
|
|
system.cpu.l2cache.mshr_cap_events::1 0 # number of times MSHR cap was activated
|
|
system.cpu.l2cache.mshr_cap_events::total 0 # number of times MSHR cap was activated
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.occ_%::0 0.013480 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_blocks::0 441.702410 # Average occupied blocks per context
|
|
system.cpu.l2cache.overall_accesses 966 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_avg_miss_latency::0 34553.941909 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::1 0 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 34553.941909 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::0 31418.568465 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_hits 2 # number of overall hits
|
|
system.cpu.l2cache.overall_miss_latency::0 33310000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::1 0 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 33310000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_rate 0.997930 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_misses 964 # number of overall misses
|
|
system.cpu.l2cache.overall_mshr_hits::0 0 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::1 0 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 0 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_miss_latency::0 30287500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 30287500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_rate::0 0.997930 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997930 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_misses::0 964 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::1 0 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 964 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.replacements::0 0 # number of replacements
|
|
system.cpu.l2cache.replacements::1 0 # number of replacements
|
|
system.cpu.l2cache.replacements::total 0 # number of replacements
|
|
system.cpu.l2cache.sampled_refs 818 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.l2cache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.l2cache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.l2cache.tagsinuse 441.702410 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.writebacks::0 0 # number of writebacks
|
|
system.cpu.l2cache.writebacks::1 0 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 0 # number of writebacks
|
|
system.cpu.memDep0.conflictingLoads 43 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores.
|
|
system.cpu.memDep0.insertedLoads 2383 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 1294 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep1.conflictingLoads 22 # Number of conflicting loads.
|
|
system.cpu.memDep1.conflictingStores 7 # Number of conflicting stores.
|
|
system.cpu.memDep1.insertedLoads 2368 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep1.insertedStores 1232 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.numCycles 28279 # number of cpu cycles simulated
|
|
system.cpu.rename.RENAME:BlockCycles 2728 # Number of cycles rename is blocking
|
|
system.cpu.rename.RENAME:CommittedMaps 9166 # Number of HB maps that are committed
|
|
system.cpu.rename.RENAME:IQFullEvents 4 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.RENAME:IdleCycles 33046 # Number of cycles rename is idle
|
|
system.cpu.rename.RENAME:LSQFullEvents 1284 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.RENAME:RenameLookups 31631 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.RENAME:RenamedInsts 25294 # Number of instructions processed by rename
|
|
system.cpu.rename.RENAME:RenamedOperands 18871 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RENAME:RunCycles 4411 # Number of cycles rename is running
|
|
system.cpu.rename.RENAME:SquashCycles 2039 # Number of cycles rename is squashing
|
|
system.cpu.rename.RENAME:UnblockCycles 1326 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RENAME:UndoneMaps 9705 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.RENAME:serializeStallCycles 679 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RENAME:serializingInsts 50 # count of serializing insts renamed
|
|
system.cpu.rename.RENAME:skidInsts 3216 # count of insts added to the skid buffer
|
|
system.cpu.rename.RENAME:tempSerializingInsts 38 # count of temporary serializing insts renamed
|
|
system.cpu.timesIdled 276 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls
|
|
system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls
|
|
|
|
---------- End Simulation Statistics ----------
|