Andreas Sandberg 0ee18f5b66 dev, arm: Initialized the iccrpr register in the GIC ... The IICRPR register in the GIC is currently not being initialized when the GIC is instantiated. Initialize to the value mandated by the architecture specification.		2015-11-11 10:18:38 +00:00
..
arch	arm: Add secure flag to TableWalker request when needed	2015-10-29 08:48:26 -04:00
base	misc: Appease clang static analyzer	2015-11-06 03:26:16 -05:00
cpu	misc: Add explicit overrides and fix other clang >= 3.5 issues	2015-10-12 04:08:01 -04:00
dev	dev, arm: Initialized the iccrpr register in the GIC	2015-11-11 10:18:38 +00:00
doc	cpu: `Minor' in-order CPU model	2014-07-23 16:09:04 -05:00
doxygen	MEM: Put memory system document into doxygen	2012-09-25 11:49:41 -05:00
kern	misc: Remove redundant compiler-specific defines	2015-10-12 04:07:59 -04:00
mem	mem: Add an option to perform clean writebacks from caches	2015-11-06 03:26:43 -05:00
proto	cpu: add support for outputing a protobuf formatted CPU trace	2015-02-16 03:32:38 -05:00
python	sim: print pid in output header	2015-10-06 17:26:50 -07:00
sim	misc: Add explicit overrides and fix other clang >= 3.5 issues	2015-10-12 04:08:01 -04:00
unittest	base: Rewrite the CircleBuf to fix bugs and add serialization	2015-08-07 09:59:19 +01:00
Doxyfile	Doxygen: Update the version of the Doxyfile	2012-10-11 06:38:42 -04:00
SConscript	sim: tag-based checkpoint versioning	2015-09-02 15:23:30 -05:00