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gem5/src/mem
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Ali Saidi 396600de10 mem: Add a gasket that allows memory ranges to be re-mapped. 
For example if DRAM is at two locations and mirrored this patch allows the
mirroring to occur.
2012-09-25 11:49:40 -05:00
..
cache AddrRange: Transition from Range<T> to AddrRange 2012-09-19 06:15:44 -04:00
config Fixes to get prefetching working again. 2009-02-16 08:56:40 -08:00
protocol Ruby: Modify Scons so that we can put .sm files in extras 2012-09-12 14:52:04 -05:00
ruby RubyPort and Sequencer: Fix draining 2012-09-23 13:57:08 -05:00
slicc ruby: avoid using g_system_ptr for event scheduling 2012-09-18 22:46:34 -05:00
abstract_mem.cc Mem: Remove the file parameter from AbstractMemory 2012-09-19 06:15:46 -04:00
abstract_mem.hh AddrRange: Transition from Range<T> to AddrRange 2012-09-19 06:15:44 -04:00
AbstractMemory.py Mem: Remove the file parameter from AbstractMemory 2012-09-19 06:15:46 -04:00
addr_mapper.cc mem: Add a gasket that allows memory ranges to be re-mapped. 2012-09-25 11:49:40 -05:00
addr_mapper.hh mem: Add a gasket that allows memory ranges to be re-mapped. 2012-09-25 11:49:40 -05:00
AddrMapper.py mem: Add a gasket that allows memory ranges to be re-mapped. 2012-09-25 11:49:40 -05:00
bridge.cc AddrRange: Transition from Range<T> to AddrRange 2012-09-19 06:15:44 -04:00
bridge.hh AddrRange: Transition from Range<T> to AddrRange 2012-09-19 06:15:44 -04:00
Bridge.py Bridge: Remove NACKs in the bridge and unify with packet queue 2012-08-22 11:39:58 -04:00
bus.cc Mem: Tidy up bus member variables types 2012-09-21 10:11:24 -04:00
bus.hh Mem: Tidy up bus member variables types 2012-09-21 10:11:24 -04:00
Bus.py Mem: Tidy up bus member variables types 2012-09-21 10:11:24 -04:00
coherent_bus.cc Port: Align port names in C++ and Python 2012-07-09 12:35:39 -04:00
coherent_bus.hh Bus: Split the bus into separate request/response layers 2012-07-09 12:35:37 -04:00
comm_monitor.cc Port: Make getAddrRanges const 2012-07-09 12:35:34 -04:00
comm_monitor.hh Port: Make getAddrRanges const 2012-07-09 12:35:34 -04:00
CommMonitor.py MEM: Add the communication monitor 2012-05-09 04:37:45 -04:00
fs_translating_port_proxy.cc mem: fix bug with CopyStringOut and null string termination. 2012-05-10 18:04:27 -05:00
fs_translating_port_proxy.hh MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
mem_object.cc Clock: Move the clock and related functions to ClockedObject 2012-08-21 05:49:01 -04:00
mem_object.hh Clock: Move the clock and related functions to ClockedObject 2012-08-21 05:49:01 -04:00
MemObject.py Clock: Move the clock and related functions to ClockedObject 2012-08-21 05:49:01 -04:00
mport.cc MEM: Separate snoops and normal memory requests/responses 2012-04-14 05:45:07 -04:00
mport.hh MEM: Separate requests and responses for timing accesses 2012-05-01 13:40:42 -04:00
noncoherent_bus.cc Port: Align port names in C++ and Python 2012-07-09 12:35:39 -04:00
noncoherent_bus.hh Bus: Split the bus into separate request/response layers 2012-07-09 12:35:37 -04:00
packet.cc Packet: Remove NACKs from packet and its use in endpoints 2012-08-22 11:39:59 -04:00
packet.hh mem: Add a gasket that allows memory ranges to be re-mapped. 2012-09-25 11:49:40 -05:00
packet_access.hh arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh 2009-09-23 08:34:21 -07:00
packet_queue.cc Port: Extend the QueuedPort interface and use where appropriate 2012-08-22 11:39:56 -04:00
packet_queue.hh MEM: Separate requests and responses for timing accesses 2012-05-01 13:40:42 -04:00
page_table.cc Fix: Address a few benign memory leaks 2012-07-09 12:35:30 -04:00
page_table.hh SE/FS: Get rid of includes of config/full_system.hh. 2011-11-18 02:20:22 -08:00
physical.cc AddrRange: Transition from Range<T> to AddrRange 2012-09-19 06:15:44 -04:00
physical.hh AddrRange: Transition from Range<T> to AddrRange 2012-09-19 06:15:44 -04:00
port.cc Port: Stricter port bind/unbind semantics 2012-08-28 14:30:27 -04:00
port.hh AddrRange: Transition from Range<T> to AddrRange 2012-09-19 06:15:44 -04:00
port_proxy.cc MEM: Remove the Broadcast destination from the packet 2012-04-14 05:45:55 -04:00
port_proxy.hh MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
qport.hh Port: Extend the QueuedPort interface and use where appropriate 2012-08-22 11:39:56 -04:00
request.hh sim: Remove FastAlloc 2012-06-05 01:23:08 -04:00
SConscript mem: Add a gasket that allows memory ranges to be re-mapped. 2012-09-25 11:49:40 -05:00
se_translating_port_proxy.cc SETranslatingPortProxy: fix bug in tryReadString() 2012-08-06 16:57:11 -07:00
se_translating_port_proxy.hh MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
simple_dram.cc DRAM: Introduce SimpleDRAM to capture a high-level controller 2012-09-21 11:48:13 -04:00
simple_dram.hh DRAM: Introduce SimpleDRAM to capture a high-level controller 2012-09-21 11:48:13 -04:00
simple_mem.cc Mem: Add a maximum bandwidth to SimpleMemory 2012-09-18 10:30:02 -04:00
simple_mem.hh Mem: Add a maximum bandwidth to SimpleMemory 2012-09-18 10:30:02 -04:00
SimpleDRAM.py DRAM: Introduce SimpleDRAM to capture a high-level controller 2012-09-21 11:48:13 -04:00
SimpleMemory.py Mem: Add a maximum bandwidth to SimpleMemory 2012-09-18 10:30:02 -04:00
tport.cc Port: Extend the QueuedPort interface and use where appropriate 2012-08-22 11:39:56 -04:00
tport.hh Port: Hide the queue implementation in SimpleTimingPort 2012-07-09 12:35:42 -04:00