61d95de4c8
SConscript: arch/isa_parser.py: cpu/base_dyn_inst.cc: Remove OOO CPU stuff. arch/alpha/faults.hh: Add fake memory fault. This will be removed eventually. arch/alpha/isa_desc: Change EA comp and Mem accessor to be const StaticInstPtrs. cpu/base_dyn_inst.hh: Update read/write calls to use load queue and store queue indices. cpu/beta_cpu/alpha_dyn_inst.hh: Change to const StaticInst in the register accessors. cpu/beta_cpu/alpha_dyn_inst_impl.hh: Update syscall code with thread numbers. cpu/beta_cpu/alpha_full_cpu.hh: Alter some of the full system code so it will compile without errors. cpu/beta_cpu/alpha_full_cpu_builder.cc: Created a DerivAlphaFullCPU class so I can instantiate different CPUs that have different template parameters. cpu/beta_cpu/alpha_full_cpu_impl.hh: Update some of the full system code so it compiles. cpu/beta_cpu/alpha_params.hh: cpu/beta_cpu/fetch_impl.hh: Remove asid. cpu/beta_cpu/comm.hh: Remove global history field. cpu/beta_cpu/commit.hh: Comment out rename map. cpu/beta_cpu/commit_impl.hh: Update some of the full system code so it compiles. Also change it so that it handles memory instructions properly. cpu/beta_cpu/cpu_policy.hh: Removed IQ from the IEW template parameter to make it more uniform. cpu/beta_cpu/decode.hh: Add debug function. cpu/beta_cpu/decode_impl.hh: Slight updates for decode in the case where it causes a squash. cpu/beta_cpu/fetch.hh: cpu/beta_cpu/rob.hh: Comment out unneccessary code. cpu/beta_cpu/full_cpu.cc: Changed some of the full system code so it compiles. Updated exec contexts and so forth to hopefully make multithreading easier. cpu/beta_cpu/full_cpu.hh: Updated some of the full system code to make it compile. cpu/beta_cpu/iew.cc: Removed IQ from template parameter to IEW. cpu/beta_cpu/iew.hh: Removed IQ from template parameter to IEW. Updated IEW to recognize the Load/Store queue. cpu/beta_cpu/iew_impl.hh: New handling of memory instructions through the Load/Store queue. cpu/beta_cpu/inst_queue.hh: Updated comment. cpu/beta_cpu/inst_queue_impl.hh: Slightly different handling of memory instructions due to Load/Store queue. cpu/beta_cpu/regfile.hh: Updated full system code so it compiles. cpu/beta_cpu/rob_impl.hh: Moved some code around; no major functional changes. cpu/ooo_cpu/ooo_cpu.hh: Slight updates to OOO CPU; still does not work. cpu/static_inst.hh: Remove OOO CPU stuff. Change ea comp and mem acc to return const StaticInst. kern/kernel_stats.hh: Extra forward declares added due to compile error. --HG-- extra : convert_revision : 594a7cdbe57f6c2bda7d08856fcd864604a6238e
140 lines
3.2 KiB
C++
140 lines
3.2 KiB
C++
#ifndef __CPU_BETA_CPU_COMM_HH__
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#define __CPU_BETA_CPU_COMM_HH__
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#include <stdint.h>
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#include <vector>
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#include "arch/alpha/isa_traits.hh"
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#include "cpu/inst_seq.hh"
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// Find better place to put this typedef.
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// The impl might be the best place for this.
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typedef short int PhysRegIndex;
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template<class Impl>
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struct SimpleFetchSimpleDecode {
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typedef typename Impl::DynInstPtr DynInstPtr;
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int size;
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DynInstPtr insts[Impl::MaxWidth];
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};
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template<class Impl>
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struct SimpleDecodeSimpleRename {
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typedef typename Impl::DynInstPtr DynInstPtr;
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int size;
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DynInstPtr insts[Impl::MaxWidth];
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};
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template<class Impl>
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struct SimpleRenameSimpleIEW {
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typedef typename Impl::DynInstPtr DynInstPtr;
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int size;
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DynInstPtr insts[Impl::MaxWidth];
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};
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template<class Impl>
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struct SimpleIEWSimpleCommit {
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typedef typename Impl::DynInstPtr DynInstPtr;
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int size;
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DynInstPtr insts[Impl::MaxWidth];
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bool squash;
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bool branchMispredict;
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bool branchTaken;
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uint64_t mispredPC;
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uint64_t nextPC;
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InstSeqNum squashedSeqNum;
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};
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template<class Impl>
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struct IssueStruct {
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typedef typename Impl::DynInstPtr DynInstPtr;
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int size;
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DynInstPtr insts[Impl::MaxWidth];
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};
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struct TimeBufStruct {
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struct decodeComm {
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bool squash;
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bool stall;
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bool predIncorrect;
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uint64_t branchAddr;
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InstSeqNum doneSeqNum;
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// Might want to package this kind of branch stuff into a single
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// struct as it is used pretty frequently.
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bool branchMispredict;
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bool branchTaken;
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uint64_t mispredPC;
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uint64_t nextPC;
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};
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decodeComm decodeInfo;
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// Rename can't actually tell anything to squash or send a new PC back
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// because it doesn't do anything along those lines. But maybe leave
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// these fields in here to keep the stages mostly orthagonal.
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struct renameComm {
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bool squash;
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bool stall;
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uint64_t nextPC;
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};
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renameComm renameInfo;
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struct iewComm {
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bool stall;
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// Also eventually include skid buffer space.
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unsigned freeIQEntries;
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};
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iewComm iewInfo;
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struct commitComm {
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bool squash;
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bool stall;
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unsigned freeROBEntries;
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bool branchMispredict;
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bool branchTaken;
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uint64_t mispredPC;
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uint64_t nextPC;
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// Think of better names here.
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// Will need to be a variety of sizes...
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// Maybe make it a vector, that way only need one object.
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// std::vector<PhysRegIndex> freeRegs;
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bool robSquashing;
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// Represents the instruction that has either been retired or
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// squashed. Similar to having a single bus that broadcasts the
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// retired or squashed sequence number.
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InstSeqNum doneSeqNum;
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// Extra bits of information so that the LDSTQ only updates when it
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// needs to.
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// bool commitIsStore;
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bool commitIsLoad;
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// Communication specifically to the IQ to tell the IQ that it can
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// schedule a non-speculative instruction.
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InstSeqNum nonSpecSeqNum;
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};
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commitComm commitInfo;
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};
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#endif //__CPU_BETA_CPU_COMM_HH__
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