Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black
96 lines
4.2 KiB
C++
96 lines
4.2 KiB
C++
// -*- mode:c++ -*-
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// Copyright (c) 2010-2011 ARM Limited
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// All rights reserved
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Gabe Black
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let {{
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header_output = decoder_output = exec_output = ""
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class SwapInst(LoadStoreInst):
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execBase = 'Swap'
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decConstBase = 'Swap'
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def __init__(self, name, Name, eaCode,
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preAccCode, postAccCode, memFlags, instFlags = []):
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super(SwapInst, self).__init__()
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self.name = name
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self.Name = Name
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self.eaCode = eaCode
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self.preAccCode = preAccCode
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self.postAccCode = postAccCode
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self.memFlags = memFlags
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self.instFlags = instFlags
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def emit(self):
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global header_output, decoder_output, exec_output
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codeBlobs = { "ea_code": self.eaCode,
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"preacc_code": self.preAccCode,
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"postacc_code": self.postAccCode }
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codeBlobs["predicate_test"] = pickPredicate(codeBlobs)
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(newHeader,
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newDecoder,
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newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
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self.memFlags, self.instFlags,
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base = 'Swap')
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header_output += newHeader
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decoder_output += newDecoder
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exec_output += newExec
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swpPreAccCode = '''
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if (!((SCTLR)Sctlr).sw) {
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return new UndefinedInstruction(machInst, false, mnemonic);
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}
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'''
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SwapInst('swp', 'Swp', 'EA = Base;',
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swpPreAccCode + 'Mem = cSwap(Op1_uw, ((CPSR)Cpsr).e);',
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'Dest = cSwap((uint32_t)memData, ((CPSR)Cpsr).e);',
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['Request::MEM_SWAP',
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'ArmISA::TLB::AlignWord',
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'ArmISA::TLB::MustBeOne'],
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['IsStoreConditional']).emit()
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SwapInst('swpb', 'Swpb', 'EA = Base;',
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swpPreAccCode + 'Mem_ub = cSwap(Op1_ub, ((CPSR)Cpsr).e);',
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'Dest_ub = cSwap((uint8_t)memData, ((CPSR)Cpsr).e);',
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['Request::MEM_SWAP',
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'ArmISA::TLB::AlignByte',
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'ArmISA::TLB::MustBeOne'],
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['IsStoreConditional']).emit()
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}};
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